DS31256 datasheet(45/183 Pages) MAXIM

45 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

45 of 183

The DS31256 has a set of three registers per DS0 channel for each port that determine how each DS0

channel is configured. These three registers are defined in Section 6.3. If the fast (52Mbps) HDLC

engine is enabled on port 0, then HDLC channel 1 is assigned to it. Likewise, HDLC channel 2 is

assigned to the fast HDLC engine on port 1 if it is enabled, and HDLC channel 2 is assigned to the fast

HDLC engine on port 2 if it is enabled.

The DS31256 contains an on-board full-featured BERT capable of generating and detecting both

pseudorandom and repeating serial bit patterns. The BERT function is a shared resource among the 16

ports on the DS31256 and can only be assigned to one port at a time. It can be used in both channelized

and unchannelized applications and at speeds up to 52MHz. In channelized applications, data can be

routed to and from any combination of DS0 channels that are being used on the port. The details on the

BERT function are covered in Section 6.5.

The Layer 1 block also contains a V.54 detector. Each of the 16 ports contains a V.54 loop pattern

detector on the receive side. The device can search for the V.54 loop-up and loop-down patterns in both

channelized and unchannelized applications at speeds up to 10MHz. In channelized applications, the

device can be configured to search for the patterns in any combination of DS0 channels. Section 6.4

describes all of the details on the V.54 detector.

DS31256 数据表(PDF) 45 Page - Maxim Integrated Products