DS31256 datasheet(89/183 Pages) MAXIM

89 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

89 of 183

Figure 9-2. Receive DMA Memory Organization

Free Data Buffer Space

Receive Free-Queue Descriptors:

Contains 32-Bit Addresses for Free Data

Buffers and their Associated

Free Packet Descriptors

Free-Queue Base Address (32)

Free-Queue End Address (16)

Free-Queue Small Buffer Start Address (16)

Free-Queue Large Buffer Host Write Pointer (16)

Free-Queue Large Buffer DMA Read Pointer (16)

Free-Queue Small Buffer DMA Read Pointer (16)

Free-Queue Small Buffer Host Write Pointer (16)

Up to 64k Dual dwords

Free-Queue Descriptors Allowed

Receive Done-Queue Descriptors:

Contains Index Pointers to

Used Packet Descriptors

Done-Queue Base Address (32)

Done-Queue End Address (16)

Done-Queue DMA Write Pointer (16)

Done-Queue Host Read Pointer (16)

Upto64kdwordsDone-Queue

Descriptors Allowed

Receive Packet Descriptors:

Contains 32-Bit Addresses

to Free Buffer as well as

Status/Control Information and

Links to Other Packet Descriptors

Descriptor Base Address (32)

Up to 64k Quad dwords

Descriptors Allowed

Used Data Buffer Space

Main Off-Board Memory

(32-Bit Address Space)

Internal Registers

DS31256 数据表(PDF) 89 Page - Maxim Integrated Products

DS31256 数据表(HTML) 89 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载