DS31256 datasheet(4/183 Pages) MAXIM

4 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

4 of 183

LIST OF FIGURES

Figure 2-1. Block Diagram....................................................................................................................................... 10

Figure 5-1. Status Register Block Diagram for SM and SV54................................................................................. 36

Figure 6-1. Layer 1 Block Diagram.......................................................................................................................... 46

Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ............................................................... 47

Figure 6-3. Layer 1 Register Set............................................................................................................................... 51

Figure 6-4. Port RAM Indirect Access ..................................................................................................................... 53

Figure 6-5. Receive V.54 Host Algorithm................................................................................................................ 58

Figure 6-6. Receive V.54 State Machine.................................................................................................................. 59

Figure 6-7. BERT Mux Diagram.............................................................................................................................. 60

Figure 6-8. BERT Register Set................................................................................................................................. 61

Figure 8-1. FIFO Example........................................................................................................................................ 75

Figure 9-1. Receive DMA Operation ....................................................................................................................... 88

Figure 9-2. Receive DMA Memory Organization.................................................................................................... 89

Figure 9-3. Receive Descriptor Example.................................................................................................................. 90

Figure 9-4. Receive Packet Descriptors.................................................................................................................... 91

Figure 9-5. Receive Free-Queue Descriptor............................................................................................................. 92

Figure 9-6. Receive Free-Queue Structure ............................................................................................................... 94

Figure 9-7. Receive Done-Queue Descriptor ........................................................................................................... 97

Figure 9-8. Receive Done-Queue Structure.............................................................................................................. 99

Figure 9-9. Receive DMA Configuration RAM..................................................................................................... 102

Figure 9-10. Transmit DMA Operation.................................................................................................................. 108

Figure 9-11. Transmit DMA Memory Organization .............................................................................................. 109

Figure 9-12. Transmit DMA Packet Handling ....................................................................................................... 110

Figure 9-13. Transmit DMA Priority Packet Handling .......................................................................................... 111

Figure 9-14. Transmit DMA Error Recovery Algorithm ....................................................................................... 113

Figure 9-15. Transmit Descriptor Example ............................................................................................................ 114

Figure 9-16. Transmit Packet Descriptors .............................................................................................................. 115

Figure 9-17. Transmit Pending-Queue Descriptor ................................................................................................. 116

Figure 9-18. Transmit Pending-Queue Structure.................................................................................................... 118

Figure 9-19. Transmit Done-Queue Descriptor...................................................................................................... 120

Figure 9-20. Transmit Done-Queue Structure ........................................................................................................ 122

Figure 9-21. Transmit DMA Configuration RAM ................................................................................................. 125

Figure 10-1. PCI Configuration Memory Map....................................................................................................... 130

Figure 10-2. PCI Bus Read..................................................................................................................................... 131

Figure 10-3. PCI Bus Write.................................................................................................................................... 132

Figure 10-4. PCI Bus Arbitration Signaling Protocol............................................................................................. 133

Figure 10-5. PCI Initiator Abort ............................................................................................................................. 133

Figure 10-6. PCI Target Retry................................................................................................................................ 134

Figure 10-7. PCI Target Disconnect....................................................................................................................... 134

Figure 10-8. PCI Target Abort................................................................................................................................ 135

Figure 10-9. PCI Fast Back-To-Back ..................................................................................................................... 136

Figure 11-1. Bridge Mode ...................................................................................................................................... 148

Figure 11-2. Bridge Mode with Arbitration Enabled ............................................................................................. 148

Figure 11-3. Configuration Mode........................................................................................................................... 149

Figure 11-4. Local Bus Access Flowchart.............................................................................................................. 152

Figure 11-5. 8-Bit Read Cycle................................................................................................................................ 155

Figure 11-6. 16-Bit Write Cycle............................................................................................................................. 156

Figure 11-7. 8-Bit Read Cycle................................................................................................................................ 157

Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle ................................................................................ 158

Figure 11-9. 8-Bit Read Cycle................................................................................................................................ 159

Figure 11-10. 8-Bit Write Cycle............................................................................................................................. 160

Figure 11-11. 16-Bit Read Cycle............................................................................................................................ 161

DS31256 数据表(PDF) 4 Page - Maxim Integrated Products

DS31256 数据表(HTML) 4 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载