DS31256 datasheet(5/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

5 of 183

Figure 11-12. 8-Bit Write Cycle............................................................................................................................. 162

Figure 12-1. Block Diagram ................................................................................................................................... 163

Figure 12-2. TAP Controller State Machine........................................................................................................... 164

Figure 13-1. Layer 1 Port AC Timing Diagram ..................................................................................................... 169

Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram................................................................. 170

Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.................................................... 172

Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) ................................ 173

Figure 13-5. PCI Bus Interface AC Timing Diagram............................................................................................. 174

Figure 13-6. JTAG Test Port Interface AC Timing Diagram................................................................................. 175

Figure 16-1. 27mm x 27mm PBGA with 256 Balls, 2oz Planes, +70

°C Ambient,

Under Natural Convection at 3.0W................................................................................................................. 178

Figure 17-1. Application Drawing Key .................................................................................................................. 179

Figure 17-2. Single T1/E1 Line Connection........................................................................................................... 179

Figure 17-3. Quad T1/E1 Connection .................................................................................................................... 180

Figure 17-4. 16-Port T1 Application ...................................................................................................................... 180

Figure 17-5. Dual T3 Application .......................................................................................................................... 181

Figure 17-6. T3 Application (512 HDLC Channels).............................................................................................. 182

Figure 17-7. T3 Application (672 HDLC Channels).............................................................................................. 183

LIST OF TABLES

Table 1-A. Data Sheet Definitions.............................................................................................................................. 7

Table 2-A. Restrictions............................................................................................................................................. 11

Table 2-B. Initialization Steps .................................................................................................................................. 12

Table 2-C. Indirect Registers.................................................................................................................................... 12

Table 3-A. Signal Description .................................................................................................................................. 13

Table 3-B. RS Sampled Edge ................................................................................................................................... 18

Table 3-C. TS Sampled Edge ................................................................................................................................... 19

Table 4-A. Memory Map Organization .................................................................................................................... 26

Table 6-A. Channelized Port Modes ........................................................................................................................ 44

Table 6-B. Receive V.54 Search Routine................................................................................................................. 57

Table 7-A. Receive HDLC Packet Processing Outcomes ........................................................................................ 67

Table 7-B. Receive HDLC Functions....................................................................................................................... 68

Table 7-C. Transmit HDLC Functions ..................................................................................................................... 68

Table 8-A. FIFO Priority Algorithm Select.............................................................................................................. 74

Table 9-A. DMA Registers to be Configured by the Host on Power-Up ................................................................. 84

Table 9-B. Receive DMA Main Operational Areas ................................................................................................. 86

Table 9-C. Receive Descriptor Address Storage ...................................................................................................... 90

Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation............................................... 93

Table 9-E. Receive Free-Queue Internal Address Storage ....................................................................................... 93

Table 9-F. Receive Done-Queue Internal Address Storage...................................................................................... 98

Table 9-G. Transmit DMA Main Operational Areas.............................................................................................. 106

Table 9-H. Done-Queue Error-Status Conditions................................................................................................... 112

Table 9-I. Transmit Descriptor Address Storage.................................................................................................... 114

Table 9-J. Transmit Pending-Queue Internal Address Storage .............................................................................. 117

Table 9-K. Transmit Done-Queue Internal Address Storage ................................................................................. 121

Table 11-A. Local Bus Signals............................................................................................................................... 147

Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting ................................................................................. 150

Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting........................................................................ 150

Table 12-A. Instruction Codes................................................................................................................................ 166

Table 16-A. Thermal Properties, Natural Convection............................................................................................ 178

Table 16-B. Thermal Properties vs. Airflow .......................................................................................................... 178

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