DS31256 datasheet(2/183 Pages) MAXIM

2 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

2 of 183

TABLE OF CONTENTS

1. MAIN FEATUERS ............................................................................................................................. 6

2. DETAILED DESCRIPTION ............................................................................................................. 7

3. SIGNAL DESCRIPTION................................................................................................................. 13

3.1

OVERVIEW/SIGNAL LIST.............................................................................................................................. 13

3.2

SERIAL PORT INTERFACE SIGNAL DESCRIPTION ......................................................................................... 18

3.3

LOCAL BUS SIGNAL DESCRIPTION .............................................................................................................. 19

3.4

JTAG SIGNAL DESCRIPTION........................................................................................................................ 22

3.5

PCI BUS SIGNAL DESCRIPTION ................................................................................................................... 22

3.6

PCI EXTENSION SIGNALS ............................................................................................................................ 25

3.7

SUPPLY AND TEST SIGNAL DESCRIPTION.................................................................................................... 25

4. MEMORY MAP ............................................................................................................................... 26

4.1

INTRODUCTION ............................................................................................................................................ 26

4.2

GENERAL CONFIGURATION REGISTERS (0XX) ............................................................................................ 26

4.3

RECEIVE PORT REGISTERS (1XX) ................................................................................................................ 27

4.4

TRANSMIT PORT REGISTERS (2XX).............................................................................................................. 27

4.5

CHANNELIZED PORT REGISTERS (3XX) ....................................................................................................... 28

4.6 HDLC REGISTERS (4XX) ............................................................................................................................. 29

4.7

BERT REGISTERS (5XX).............................................................................................................................. 29

4.8

RECEIVE DMA REGISTERS (7XX)................................................................................................................ 29

4.9

TRANSMIT DMA REGISTERS (8XX)............................................................................................................. 30

4.10

FIFO REGISTERS (9XX) ........................................................................................................................... 30

4.11

PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX) ...................................................... 31

4.12

PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX) ...................................................... 31

5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT.................................. 32

5.1

MASTER RESET AND ID REGISTER DESCRIPTION ....................................................................................... 32

5.2

MASTER CONFIGURATION REGISTER DESCRIPTION.................................................................................... 32

5.3

STATUS AND INTERRUPT ............................................................................................................................. 34

5.3.1

General Description of Operation ...................................................................................................... 34

5.3.2

Status and Interrupt Register Description .......................................................................................... 37

5.4

TEST REGISTER DESCRIPTION ..................................................................................................................... 43

6. LAYER 1............................................................................................................................................ 44

6.1

GENERAL DESCRIPTION............................................................................................................................... 44

6.2

PORT REGISTER DESCRIPTIONS ................................................................................................................... 48

6.3

LAYER 1 CONFIGURATION REGISTER DESCRIPTION ................................................................................... 51

6.4

RECEIVE V.54 DETECTOR............................................................................................................................ 56

6.5

BERT........................................................................................................................................................... 60

6.6

BERT REGISTER DESCRIPTION ................................................................................................................... 61

7. HDLC ................................................................................................................................................. 67

7.1

GENERAL DESCRIPTION............................................................................................................................... 67

7.2 HDLC REGISTER DESCRIPTION................................................................................................................... 69

8. FIFO ................................................................................................................................................... 74

8.1

GENERAL DESCRIPTION AND EXAMPLE ...................................................................................................... 74

8.1.1

Receive High Watermark .................................................................................................................... 76

8.1.2

Transmit Low Watermark ................................................................................................................... 76

8.2

FIFO REGISTER DESCRIPTION..................................................................................................................... 76

9. DMA ................................................................................................................................................... 83

9.1

INTRODUCTION ............................................................................................................................................ 83

9.2

RECEIVE SIDE .............................................................................................................................................. 85

9.2.1

Overview ............................................................................................................................................. 85

9.2.2

Packet Descriptors.............................................................................................................................. 90

9.2.3

Free Queue ......................................................................................................................................... 92

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