DS31256 datasheet(151/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Bridge Mode Bus Transaction Timing

When the local bus is operated in PCI bridge mode, the bus transaction time can be determined either

from an external ready signal (

LRDY) or from the PCI bridge mode control register (LBBMC), which

allows a bus transaction time of 1 to 11 LCLK cycles. If the total access time to the local bus exceeds 16

PCLK cycles, the PCI access times out and a PCI target retry is sent to the host. This only occurs when

LRDY has not been detected within 9 clocks. If this happens, the local bus error (LBE) status bit in the

status master (SM) register is set. Additional details about the LBE status bit can be found in Section 5.

More details about transaction timing can be found in Figure 10-4 and the timing examples in

Section 11.3.

Bridge Mode Interrupt

In the PCI bridge mode, the local bus can detect an external interrupt through the

LINT signal. If the

local bus detects that the

LINTA signal has been asserted, it then sets the LBINT status bit in the status

master (SM) register. Setting this status bit can cause a hardware interrupt to occur at the PCI bus

through the

PINTA signal. This interrupt can be masked through the ISM register. See Section 5 for

more details.

11.1.2 Configuration Mode

In configuration mode, the local bus is used only to configure the device and obtain status information

from the device. It is also used to configure the PCI configuration registers and therefore the PCI bus

signal PIDSEL is disabled when the local bus is in the configuration mode. The DS31256 PCI

configuration registers can't be accessed via the PCI bus when the DS31256 is in Configuration mode

(LMS=1). In this mode no device registers are accessible via the PCI bus.

Data cannot be passed from the local bus to the PCI bus in this mode. The PCI bus is only used as a

high-speed I/O bus for the HDLC packet data. In this mode, bus arbitration, bus format, and the user-

settable bus transaction time features are disabled. All bus accesses are based on 16-bit addresses and 16-

bit data in this mode. The upper four addresses (LA[19:16]) are ignored and 8-bit data accesses are not

allowed. See Section 13 for the AC timing requirements.

DS31256 数据表(PDF) 151 Page - Maxim Integrated Products