CS8952 datasheet(59/82 Pages) CIRRUS

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CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

6.18

Self Status Register - Address 19h

Link OK

Power

Down

Receiving

Data

Descrambler

Lock

Disable CRS

on Time-out

Auto-Neg

Enable Status

PAUSE

FEFI Enable

765

4321

Full Duplex

10BASE-T

Mode

CIM Status

PHY Address

BIT

NAME

TYPE

RESET

DESCRIPTION

Link OK

Read Only

When set, this bit indicates that a valid link connec-

tion has been detected. The type of link established

may be determined from bits 6, 7, and 9. When clear,

this bit indicates that a valid link connection does not

exist. This bit may be used to determine the current

status of the link.

Power Down

Read Only

When high, this bit indicates that the CS8952 is in a

low power state.

Receiving Data

Read Only

This bit is high whenever the CS8952 is receiving

valid data. It is a direct copy of the state of the

RX_DV pin accessible by software.

Descrambler Lock

Read Only

When high, this bit indicates that the descrambler

has successfully locked to the scrambler seed of the

far-end transmitter and is able to descramble

received data.

Disable CRS on

Time-out

Read/Write Reset to the logic

inverse of the

valueonthe

REPEATER pin.

This bit controls the state of the CRS pin upon a

descrambler time-out. When set, CRS will be forced

low upon a descrambler time-out, and will not be

released until the descrambler has re-acquired syn-

chronization.

Auto-Neg Enable

Status

Read Only

If auto-negotiation

is enabled via the

AN[1:0] pins, reset

to 1; otherwise,

reset to 0.

This bit reflects the value of bit 12 in the Basic Mode

Control Register (address 00h). When set, it indi-

cates that auto-negotiation has been enabled. When

clear, this bit indicates that the mode of the CS8952

has been forced to that indicated by bits 6, and 7.

PAUSE

Read Only

When set, this bit indicates that the Flow-Control

PAUSE function has been negotiated. This indicates

that both the local device and the link partner have

advertised this capability.

FEFI Enable

Read/Write 0

This bit controls the Far-End Fault Generate and

Detect state machines. When this bit is set and auto-

negotiation is disabled (bit 10 is clear), both state

machines are enabled. When clear, this bit disables

both state machines.

Full Duplex

Read Only

If a full duplex

mode is enabled

via the AN[1:0]

pins, reset to 1;

otherwise, reset to

When set, this bit indicates that the CS8952 has

been configured for Full-Duplex operation.

10BASE-T Mode

Read Only

When set, this bit indicates that the CS8952 has

been configured for 10 Mb/s operation.

CS8952 数据表(PDF) 59 Page - Cirrus Logic

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CS8952 数据表(PDF) 59 Page - Cirrus Logic

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