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CS8952 数据表(PDF) 43 Page - Cirrus Logic |
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CS8952 数据表(HTML) 43 Page - Cirrus Logic |
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43 / 82 page ![]() CS8952 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 43 11 DCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the DCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 10 FCCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the FCCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 9 RECR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the RECR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 8 Remote Loopback Fault Read/Write 0 When set, an interrupt will be generated if the elastic buffer in the PMA is under-run or over-run during Remote Loopback. This should not occur for normal length 802.3 frames. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 7 Reset Complete Read/Write 1 When set, an interrupt will be generated once the digital and analog sections have been reset, and a calibration cycle has been performed. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 6 Jabber Detect Read/Write 0 When set, an interrupt will be generated when a Jab- ber condition is detected by the 10BASE-T MAU. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. BIT NAME TYPE RESET DESCRIPTION |
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