CS8952 datasheet(35/82 Pages) CIRRUS

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CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Auto-Neg Ability

Read Only

This bit indicates that the CS8952 has auto-negotia-

tion capability. Therefore this bit will always read

back a value of 1.

Link Status

Read Only

When set, this bit indicates that a valid link has been

established. Upon a link failure, this bit is cleared and

latched. It will remain cleared until this register is

read.

Jabber Detect

Read Only

In 10BASE-T mode, if the last transmission is longer

than 105 ms, then the packet output is terminated by

the jabber logic and this bit is set. If JabberiE (Inter-

rupt Mask Register (address 10h), bit 3) is set, an MII

Interrupt will be generated.

This bit is implemented with a latching function so

that the occurrence of a jabber condition causes it to

become set until it is cleared by a read to this regis-

ter, a read to the Interrupt Status Register (address

11h), or a reset.

No jabber detect function has been defined for

100BASE-TX.

Extended Capability Read Only

This bit indicates that an extended register set may

be accessed (registers beyond address 01h). This bit

always reads back a value of 1.

BIT

NAME

TYPE

RESET

DESCRIPTION

CS8952 数据表(PDF) 35 Page - Cirrus Logic

CS8952 数据表(HTML) 35 Page - Cirrus Logic

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CS8952 数据表(PDF) 35 Page - Cirrus Logic

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