CS8952 datasheet(66/82 Pages) CIRRUS

66 / 82 page

CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

7.7

General Layout Recommendations

The following PCB layout recommendations will

help ensure reliable operation of the CS8952 and

good EMC performance.

•

Use a multilayer Printed Circuit Board with at

least one ground and one power plane. A typi-

cal +5V MII application would be as follows:

Layer 1: (top) Components and first choice sig-

nal routing

Layer 2: Ground

Layer 3: Power (+5V)

Layer 4: (bottom) Second choice signal rout-

ing, bypass components

•

Place transformer TI as close to the RJ45 connec-

tor as possible with the secondary (network) side

facing the RJ45 and the primary (chip) side facing

the analog side (pins 76-100) of CS8952. Place

the CS8952inturnas close to T1 as possible.

•

Use the bottom layer for signal routing as a sec-

ond choice. You may place all components on

the top layer. However, bypass capacitors are

optimally placed as close to the chip as possible

and may be best located underneath the

CS8952 on the bottom layer. Termination com-

ponents at the RJ-45 and fiber transceiver may

also be optimally placed on the bottom layer.

•

Connect a 0.1

µF bypass capacitor to each

CS8952 VDD and VDD_MII pin. Place it as

close to its corresponding power pin as possible

and connect the other lead directly to the

ground plane.

•

The 4.99K reference resistor should be placed

as close to the RES pin as possible. Connect the

other end of this resistor to the ground plane us-

ing a via. Connect the adjacent VSS pins (pins

85 and 87) to the grounded end of the resistor

forming a shield as illustrated in Figure 8.

•

Controlled impedance is necessary for critical

signals

TX+/-,

RX+/-,

TX_NRZ+/-,

and

RX_NRZ+/-. These should be run as microstrip

transmission lines (100

Ωdifferential, 50 Ωsin-

gle-ended). The MII signals should be 68

Ωmi-

crostrip transmission lines. (For short MII

signal paths one may standardize on a given

trace width for all traces without significant

degradation in signal integrity.)

•

Avoid routing traces other than the TX and RX

signals under transformer T1 and the RJ45 con-

nector. Signals may run on the bottom side un-

derneath the CS8952 as long as they stay away

from critical analog traces.

•

Connect all CS8952 ground and power pins di-

rectly to the ground and power planes, respec-

tively. Note: The VDD_MII power pins may

need their own power plane or plane segment in

+3.3 V MII applications.

•

Depending on the orientation and location of

the transformer, the CS8952, and the RJ-45,

and on whether the application is for a NIC or a

switch,the RX andTXpairs mayneedto cross.

This should be done by changing layers on a

pair by pair basis only, using the minimum

number of vias, and making sure that each trace

within a pair “sees” the same path as its peer.

Figure 6 shows the CS8952 in a NIC or adapter

configuration. It may be configured for a hub or

repeater application by changing the wiring to

the RJ-45 as shown in Table 8.

•

Differential pair transmission lines should be

routed close together (one trace width spacing

edge-to-edge) and kept at least two trace widths

away from other traces, components, etc. TX

and RX pairs should be routed away from each

other and may use opposite sides of the PCB as

necessary, Each member of the differential pair

should “see” the same PCB terrain as its peer.

•

Unused spaces on the signal layers should be

filled with ground fill (pour). Vias should con-

nect the ground patches to the ground plane.

This is especially recommended (symmetrical-

CS8952 数据表(PDF) 66 Page - Cirrus Logic

CS8952 数据表(HTML) 66 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表下载