CS8952 datasheet(27/82 Pages) CIRRUS

27 / 82 page

CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

STATUS Pins

COL - Collision indication, valid only for

half duplex modes.

CRS - Carrier Sense indication

SERIAL MANAGEMENT Pins

MDIO - a bi-directional serial data path

MDC - clock for MDIO (16.7 MHz max)

MII_IRQ - Interrupt indicating change in

the Interrupt Status Register (address 11h)

RECEIVE DATA Pins

RXD[3:0] - Parallel data output path

RX_CLK - Recovered clock output

RX_DV - Indicates when receive data is

present and valid

RX_ER - Indicates presence of error in re-

ceived data

RX_EN - Can be used to tri-state receiver

output pins

TRANSMIT DATA Pins

TXD[3:0] - Parallel data input path

TX_CLK - Transmit clock

TX_EN - Indicates when transmit data is

present and valid

TX_ER - Request to transmit a 100BASE-

T HALT symbol, ignored for 10BASE-T

operation.

The interface uses TTL signal levels, which are

compatible with devices operating at a nominal

supply voltage of either 5.0 or 3.3 volts. It is capa-

ble of supporting either 10 Mb/s or 100 Mb/s data

rates transparently. That is, all signaling remains

identical at either data rate; only the nominal clock

frequency is changed.

4.1

MII Frame Structure

Data frames transmitted through the MII have the

following format:

Each frame is preceded by an inter-frame gap. The

inter-frame gap is an unspecified time during

which no data activity occurs on the media as indi-

cated by the de-assertion of CRS for the receive

path and TX_EN for the transmit path.

The Preamble consists of seven bytes of 10101010.

The Start of Frame Delimiter consists of a single

byte of 10101011.

Data may be any number of bytes.

The End of Frame Delimiter is conveyed by the de-

assertion of RX_DV and TX_EN for receive and

transmit paths, respectively.

Transmission and/or reception of each byte of data

is done one nibble at a time in the following order:

4.2

MII Receive Data

The presence of recovered data on the RXD[3:0]

bus is indicated by the assertion of RX_DV.

RX_DV will remain asserted from the beginning of

the preamble (or Start of Frame Delimiter if pream-

ble is not used) to the End of Frame Delimiter.

Once RX_DV is asserted, valid data will be driven

Preamble

(7 Bytes)

Start of

Frame

Delimiter

(1 Byte)

Data

End of

Frame

Delimiter

MII

LSB

MSB

Nibble

Stream

MAC’s Serial Bit Stream

First Bit

First

Second

Nibble

D1 D2 D3 D4 D5 D6 D7

LSB

MSB

CS8952 数据表(PDF) 27 Page - Cirrus Logic

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