CS8952 datasheet(30/82 Pages) CIRRUS

30 / 82 page

CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

A read transaction is indicated by an Opcode of 10

andawrite by01.

The PHY Address is five bits, with the most signif-

icant bit sent first. If the PHY address included in

the frame is not 00000 or does not match the PHY-

AD field of the Self Status Register (address 19h),

the rest of the frame is ignored.

The register address is five bits, with the most sig-

nificant bit sent first, and indicates the CS8952 reg-

ister to be written to/read from.

The Turnaround time is a two bit time spacing be-

tween when the MAC drives the last register ad-

dress bit onto MDIO and the data field of a

management frame in order to avoid contention

during a read transaction. For a read transaction,

the MAC should tri-state the MDIO pin beginning

on the first bit time, and the CS8952 will begin

driving the MDIO signal to a logic ZERO during

the second bit time. During write transactions,

since the MDIO direction does not need to be re-

versed, the MAC will drive the MDIO to a logic

ONE for the first bit time and a logic ZERO for the

second.

The data field is always 16 bits in length, with the

most significant bit sent first.

5. CONFIGURATION

The CS8952 can be configured in a variety of ways.

All control and status information can be accessed

via the MII Serial Management Interface. Addi-

tionally, many configuration options can be set at

power-up or reset times via individual control lines.

Some configuration capabilities are available at

any time via individual control lines.

5.1

Configuration At Power-up/Reset

Time

At power-up and reset time, the following pins are

5.2

Configuration Via Control Pins

The following pins are for dedicated control signals

and can be used at any time to configure the

CS8952.

5.3

Configuration via the MII

The CS8952 supports configuration by software

control through the use of 16-bit configuration and

status registers accessed via the MDIO/MDC pins

(MII Management Interface). The first seven regis-

ters are defined by the IEEE 802.3 specification.

Additional registers extend the register set to pro-

vide enhanced monitoring and control capabilities.

6. CS8952 REGISTERS

The CS8952 register set is comprised of the 16-bit

status and control registers described below. A de-

tailed description each register follows.

Pin Name

Function

10BT_SER

Select 10BASE-T serial mode

AN[1:0]

Select auto-negotiation mode

BP4B5B

Bypass 4B5B coders

BPALIGN

Bypass 4B5B coders and scramblers

BPSCR

Bypass scramblers, enter FX mode

ISODEF

Electrically isolate MII after reset

LPSTRT

Start in low power mode

PHYAD[4:0]

Set MII PHY address

REPEATER

Control definition of CRS pin, enable

carrier integrity monitor and SQE func-

tion

MII_DRV

Set MII driver strength

TCM

Set TX_CLK mode

TXSLEW[1:0] Set 100BASE-TX transmitter output

slew rate

Pin Name

Function

LPBK

Enter loopback mode

PWRDN

Enter power-down mode

RESET

Reset

Description

Type

Basic Mode Control Register

Read/Write

Basic Mode Status Register

Read-Only

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