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CS8952 数据表(PDF) 45 Page - Cirrus Logic |
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CS8952 数据表(HTML) 45 Page - Cirrus Logic |
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45 / 82 page  CS8952 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 45 6.10 Interrupt Status Register - Address 11h This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self- clearing, and will thus be cleared upon readout. 15 14 13 12 11 10 9 8 CIM Link Unstable Link Status Change Descrambler Lock Change Premature End Error DCR Rollover FCCR Rollover RECR Rollover Remote Loopback Fault 765 4321 0 Reset Complete Jabber Detect Auto-Neg Complete Parallel Detection Fault Parallel Fail Remote Fault Page Received Reserved BIT NAME TYPE RESET DESCRIPTION 15 CIM Link Unstable Read Only 0 When set, this bit indicates that an unstable link con- dition was detected by the Carrier Integrity Monitor function. 14 Link Status Change Read Only 0 When set, this bit indicates that a change has occurred to the status of the link. The Self Status Register (address 19h) may be read to determine the current status of the link. 13 Descrambler Lock Change Read Only 0 When set, this bit indicates that a change has occurred in the status of the descrambler. The Self Status Register (address 19h) may be read to deter- mine the current status of the scrambler lock. 12 Premature End Error Read Only 0 This bit is set when a premature end of frame is detected for 100 Mb/s operation. A premature end is defined as two consecutive IDLE patterns detected in a frame prior to the End of Stream Delimiter. 11 DCR Rollover Read Only 0 This bit is set when the MSB of the Disconnect Count Register (address 12h) becomes set. This should provide ample warning to the management layer so that the DCR may be read before rolling over. 10 FCCR Rollover Read Only 0 This bit is set when the MSB of the False Carrier Count Register (address 13h) becomes set. This should provide ample warning to the management layer so that the FCCR may be read before saturat- ing. 9 RECR Rollover Read Only 0 This bit is set when the MSB of the Receive Error Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over. |
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