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CS8952 数据表(PDF) 7 Page - Cirrus Logic

部件名 CS8952
功能描述  CrystalLAN 100BASE-X and 10BASE-T Transceiver
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8952 数据表(HTML) 7 Page - Cirrus Logic

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CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
7
10BASE-T CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Interface
Transmitter Differential Output Voltage (Peak)
VOD
2.2
-
2.8
V
Receiver Normal Squelch Level (Peak)
VISQ
300
-
525
mV
Receiver Low Squelch Level (LoRxSquelch bit
set)
VSQL
125
-
290
mV
10BASE-T Transmitter
TXD Pair Jitter into 100
Ω Load
tTTX1
--
8
ns
TXD Pair Return to
≤50 mV after Last Positive
Transition
tTTX2
--
4.5
µs
TXD Pair Positive Hold Time at End of Packet
tTTX3
250
-
-
ns
10BASE-T Receiver
Allowable Received Jitter at Bit Cell Center
tTRX1
-
-
+/-13.5
ns
Allowable Received Jitter at Bit Cell Boundary
tTRX2
-
-
+/-13.5
ns
10BASE-T Link Integrity
First Transmitted Link Pulse after Last Transmit-
ted Packet
tLN1
15
16
17
ms
Time Between Transmitted Link Pulses
tLN2
15
16
17
ms
Width of Transmitted Link Pulses
tLN3
60
-
200
ns
Minimum Received Link Pulses Separation
tLN4
257
ms
Maximum Received Link Pulse Separation
tLN5
25
52
150
ms
Last Receive Activity to Link Fail (Link Loss
Timer)
tLN6
50
52
150
ms
10Base-T Jabber/Unjabber Timing
Maximum Transmit Time
-
105
-
ms
Unjabber Time
-
406
-
ms
TXD±
RXD±
LINKLED
t
LN1
t
LN3
t
LN2
t
LN5
t
LN4
t
LN6
RXD±
t
RTX1
t
RTX2
t
RTX3
tRTX4
Carrier Sense
(Internal)
TXD±
t
TTX1
t
TTX3
t
TTX2



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