CS8952 datasheet(72/82 Pages) CIRRUS

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CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

When theTCM pinishighonpower-upor reset,the CLK25pin maybeusedasasource for the

TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally.

TX_CLK should have the following nominal frequency:

TX_EN - Transmit Enable. Input, Pin 43.

Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is selected,

TX_ENmustbepulleduptoVDD_MII.

TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38.

When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted

simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins

and transmit one or more 100 Mb/s HALT symbols in its place. In 10 Mb/s mode, TX_ER has no effect

on the transmitted data.

If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of the five-bit

code group.

TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44.

Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be presented

on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In 10 Mb/s serial

mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored.

When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of the five-bit

code-group.

Control and Status Pins

10BT_SER - 10 Mb/s Serial Mode Select. Input, Pin 23.

When asserted high during power-up or reset and 10 Mb/s operation is selected, serial data will be

transferred on pins RXD0 and TXD0. When low during power-up or reset and 10 Mb/s operation is

selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This pin is ignored during

100 Mb/s operation.

10 Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-T Status

At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status Register

(address 1Bh). This pin includes a weak internal pull-down (> 20 K

Ω), or the value may be set by an

external 4.7 K

Ω pull-up or pull-down resistor.

AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57.

These three-level input pins are sampled during power-up or reset. They control the forced or

advertised auto-negotiation operating modes. If one of these pins is left unconnected, internal logic pulls

its signal to a mid-range value, 'M'.

Speed

10BT_SER pin

Nominal frequency

100 Mb/s

n/a

25 MHz

10 Mb/s

low (parallel)

2.5 MHz

10 Mb/s

high (serial)

10 MHz

AN1 pin

AN0 pin

Speed

Forced/Auto

Full/Half Duplex

10 Mb/s

Forced

Half

CS8952 数据表(PDF) 72 Page - Cirrus Logic

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