AD9739-R2-EBZ datasheet(26/50 Pages) AD

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AD9739

Data Sheet

Rev. E | Page 26 of 50

DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE

Table 19. Data Receiver Controller_Data Sample Delay Value Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x11

SMP_DEL[1:0]

[7:6]

R/W

0xDD

Controller enabled: the 10-bit value (with a maximum of 332) represents the start

value for the delay line used by the state machine to sample data. Leave at the default

setting of 167, which represents the midpoint of the delay line. Controller disabled:

the value sets the actual value of the delay line.

0x12

SMP_DEL[9:2]

[7:0]

R/W

0x29

DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION

Table 20. Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x13

DCI_DEL[3:0]

[7:4]

R/W

0111

Refer to the DCI_DEL description in Register 0x14.

FINE_DEL_SKEW

[3:0]

R/W

0001

A 4-bit value sets the difference (that is, window) for the DCI PRE and POST

sampling clocks. Leave at the default value of 1 for a narrow window.

0x14

CLKDIVPH[1:0]

[7:6]

R/W

Relative phase of internal divide-by-4 circuit. This feature allows phase rotation in

90° increments (that is, 1 count) to extend Rx controllers locking range for clock

rates between 0.8 GSPS to 1.6 GSPS (only valid with sync controller disabled).

DCI_DEL[9:4]

[5:0]

R/W

001010

Controller enabled: the 10-bit value (with a maximum of 332) represents the start

value for the delay line used by the state machine to sample the DCI input. Leave

at the default setting of 167, which represents the midpoint of the delay line.

Controller disabled: the value sets the actual value of the delay line.

0x15

SYNC GAIN[1:0]

[7:6]

R/W

Sets the sync tracking gain (optimal value is 1).

SYNCOUT_PH[1:0]

[5:4]

R/W

Readback of the present SYNC_OUT phase selection.

LCKTHR[3:0]

[3:0]

R/W

0000

Sets the difference between the sample and DCI delays to lock (optimal value is 2).

0x16

SYNCO_DEL[6:0]

[6:0]

R/W

0x00

Sets the sync output delay value when the synch controller is disabled; otherwise,

is the read status of the sync output delay value when sync is enabled.

0x17

SYNCSH_DEL[0]

[7]

R/W

0x00

Sets the sync setup and hold delay value when the synch controller is disabled;

otherwise, is the read status of sync setup and hold value when sync is enabled.

0x18

SYNCSH_DEL[8:1]

[7:0]

R/W

0x00

Sets the sync setup and hold delay value when the synch controller is disabled;

otherwise, is the read status of sync setup and hold value when sync is enabled.

DATA RECEIVER CONTROLLER_DELAY LINE STATUS AND SYNC CONTROLLER SYNC_OUT STATUS

Table 21. Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x19

SMP_DEL[1:0]

[7:6]

The actual value of the DCI and data delay lines determined by the data receiver

controller (when enabled) after the state machine completes its search and enters

track mode. Note that these values should be equal.

SYNCOUT_PH provides phase status (0/90/180/270) of phase select mux, while

CLKDIVPH provides phase status of data receiver controller (Register 0x14).

0x1A

SMP_DEL[9:2]

[7:0]

0x00

0x1B

SYNCOUT_PH[1:0]

3:2

CLKDIV PH[1:0]

1:0

DCI_DEL[1:0]

[7:6]

0x1C

DCI_DEL[9:2]

[7:0]

0x00

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