AD9739-R2-EBZ datasheet(6/50 Pages) AD

6 / 50 page

AD9739

Data Sheet

Rev. E | Page 6 of 50

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I

OUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-

1996 reduced range link, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, V

COM

825

1575

Logic High Differential Input Threshold, V

IH_DTH

175

400

Logic Low Differential Input Threshold, V

IL_DTH

−175

−400

Receiver Differential Input Impedance, R

120

Ω

Input Capacitance

1.2

LVDS Input Rate

1250

MSPS

LVDS Minimum Data Valid Period, t

VALID (See Figure 41)

344

LVDS CLOCK INPUT (DCI and SYNC_IN)2

Input Common-Mode Voltage Range, V

COM

825

1575

Logic High Differential Input Threshold, V

IH_DTH

175

400

Logic Low Differential Input Threshold, V

IL_DTH

−175

−400

Receiver Differential Input Impedance, R

120

Ω

Input Capacitance

1.2

Maximum Clock Rate

625

MHz

LVDS CLOCK OUTPUT (DCO and SYNC_OUT)3

Output Voltage High (x_P or x_N)

1375

Output Voltage Low (x_P or x_N)

1025

Output Differential Voltage, |V

OD|

150

200

250

Output Offset Voltage, V

1150

1250

Output Impedance, Single-Ended, R

100

120

Ω

O Single-Ended Mismatch

Maximum Clock Rate

625

MHz

1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.

2 DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.

3 DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.

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