AD9739-R2-EBZ datasheet(48/50 Pages) AD

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AD9739

Data Sheet

Rev. E | Page 48 of 50

Table 31. Recommended SPI Initialization with SYNC Controller Disabled

Step

Address (Hex)

Write Value

Comments

0x00

Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto

Bits[2:0] because the MSB/LSB format can be unknown at power-up.

0x00

0x20

Software reset to default SPI values.

0x00

Clear the reset bit.

0x22

0x0F

Set the common-mode voltage of DACCLK_P and DACCLK_N inputs.

0x23

0x0F

0x24

0x30

Configure the mu controller. Refer to Table 28 for recommended target mu slope and

phase settings vs. clock rate.

0x25

0x80

0x27

0x44

0x28

0x6C

0x29

0xCB

0x26

0x02

0x26

0x03

Enable the mu controller search and track mode.

Not applicable

Wait for 160k × 1/f

DATA cycles.

0x2A

Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop

is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three

before breaking out of the loop and reporting a mu lock failure.

Not applicable

Ensure that the AD9739 is fed with DCI clock input from the data source.

0x13

0x72

Set FINE_DEL_SKEW to 2.

0x10

0x00

Disable the data Rx controller before enabling it.

0x10

0x02

Enable the data Rx controller for loop and IRQ.

0x10

0x03

Enable the data Rx controller for search and track mode.

Not applicable

Wait for 135 K × 1/f

DATA cycles.

0x21

Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop

is locked and tracking. If it is not locked and tracking, advance the CLKDIVPH[1:0] phase

in Register 0x14, Bit[7:6] before proceeding to Step 17 to repeat attempt. Limit attempts

to three before breaking out of the loop and reporting an Rx data lock failure.

0x06, 0x07

0x00, 0x02

Optional: modify the TxDAC I

OUTFS setting (the default is 20 mA).

0x08

0x00

Optional: modify the TxDAC operation mode (the default is normal mode).

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