AD9739-R2-EBZ datasheet(24/50 Pages) AD

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AD9739

Data Sheet

Rev. E | Page 24 of 50

SPI PORT CONFIGURATION AND SOFTWARE RESET

Table 10. SPI Port Configuration and Software Reset Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x00

SDIO_DIR

R/W

0 = 4-wire SPI, 1 = 3-wire SPI.

LSB/MSB

R/W

0 = MSB first, 1 = LSB first.

Reset

R/W

Software reset is recommended before modification of other SPI registers from the default

setting. Setting the bit to 1 causes all registers (except 0x00) to be set to the default setting.

Setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers

from the default setting.

POWER-DOWN LVDS INTERFACE AND TXDAC®

Table 11. Power-Down LVDS Interface and TxDAC Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x01

LVDS_DRVR_PD

R/W

Power-down of the LVDS drivers/receivers and TxDAC.

0 = enable, 1 = disable.

LVDS_RCVR_PD

R/W

CLK_RCVR_PD

R/W

DAC_BIAS_PD

R/W

CONTROLLER CLOCK DISABLE

Table 12. Controller Clock Disable Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x02

CLKGEN_PD

R/W

Internal CLK distribution enable:

0 = enable, 1 = disable.

REC_CNT_CLK

R/W

LVDS receiver (REC_CNT_CLK) and mu controller clock disable (MU_CNT_CLK).

0 = disable, 1 = enable.

MU_CNT_CLK

R/W

INTERRUPT REQUEST (IRQ) ENABLE/STATUS

Table 13. Interrupt Request (IRQ) Enable/Status Register

Address

(Hex)

Name

Bit

R/W

Default

Setting

Comments

0x03

SYNC_LST_EN

This register enables the sync, mu, and LVDS Rx controllers to update their

corresponding IRQ status bits in Register 0x04, which defines whether the controller is

locked (LCK) or unlocked (LST).

0 = disable (resets the status bit).

1 = enable.

SYNC_LCK_EN

MU_LST_EN

MU_LCK_EN

RCV_LST_EN

RCV_LCK_EN

0x04

SYNC_LST_IRQ

This register indicates the status of the controllers. For LCK_IQR bits: 0 = lost locked, 1

= locked. For LST_IQR bits: 0 = not lost locked, 1 = unlocked. Note that, if the

controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing

0, followed by another write of 1 to enable.

SYNC_LCK_IRQ

MU_LST_IRQ

MU_LCK_IRQ

RCV_LST_IRQ

RCV_LCK_IRQ

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