AD9739-R2-EBZ datasheet(34/50 Pages) AD

34 / 50 page

AD9739

Data Sheet

Rev. E | Page 34 of 50

Table 27. Example of LVDS Input Levels

Applied Voltages

Resulting Differential Voltage

Resulting Common-Model Voltage

VP (V)

VN (V)

VP, N

VCOM

Logic Bit Binary Equivalent

1.4

1.0

+0.4 V

1.2 V

1.0

1.4

−0.4 V

1.2 V

1.0

0.8

+200 mV

900 mV

0.8

1.0

−200 mV

900 mV

MU CONTROLLER

A delay lock loop (DLL) is used to optimize the timing between

the internal digital and analog domains of the AD9739 such

that data is successfully transferred into the TxDAC core at rates

of up to 2.5 GSPS. As shown in Figure 48, the DAC clock is split

into an analog and a digital path with the critical analog path

leading to the DAC core (for minimum jitter degradation) and

the digital path leading to a programmable delay line. Note that

the output of this delay line serves as the master internal digital

clock from which all other internal and external digital clocks

are derived. The amount of delay added to this path is under the

control of the mu controller, which optimizes the timing between

these two clock domains and continuously tracks any variation

(once in track mode) to ensure proper data hand-off.

14-BIT

DATA

14-BIT

DATA

IOUTP

IOUTN

DIGITAL

CIRCUITRY

ANALOG

CIRCUITRY

DELAY

DAC

CLOCK

PHASE

DETECTOR

DELAY

CONTROLLER

Figure 48. Mu Delay Controller Block Diagram

The mu controller adjusts the timing relationship between the

digital and analog domains via a tapped digital delay line having

a nominal total delay of 864 ps. The delay value is programmable

to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL

time delay maps to a phase offset for a fixed clock frequency,

the control loop essentially compares the phase relationship

between the two clock domains and adjusts the phase (that is, via a

tapped delay line) of the digital clock such that it is at the desired

fixed phase offset (SET_PHS) from the critical analog clock.

120

160

200

240

280

320

360

400

440

SEARCH STARTING

LOCATION

GUARD

BAND

GUARD

BAND

MU DELAY

DESIRED

PHASE

Figure 49. Typical Mu Phase Characteristic Plot at 2.4 GSPS

Figure 49 maps the typical mu phase characteristic at 2.4 GSPS vs.

the 9-bit digital delay setting (MUDEL). The mu phase scaling

is such that a value of 16 corresponds to 180 degrees. The critical

keep-out window between the digital and analog domains occurs

at a value of 0 (but can extend out to 2 depending on the clock

rate). The target mu phase (and slope) is selected to provide

optimum ac performance while ensuring that the mu controller

for any device can establish and maintain lock. For example,

while a slope and phase setting of −6 is considered optimum

for operation between 1.6 GSPS and 2.5 GSPS, other values are

required below 1.6 GSPS.

120

160

200

240

280

320

360

400

440

DELAY LINE TAP

NOM_P1

SLOW_P1

FAST_P1

Figure 50. Mu Phase Characteristics of Three Devices from Different Process

Lots at 1.2 GSPS

AD9739-R2-EBZ 数据表(PDF) 34 Page - Analog Devices

AD9739-R2-EBZ 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载