AD9739-R2-EBZ datasheet(21/50 Pages) AD

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Data Sheet

AD9739

Rev. E | Page 21 of 50

The AD9739 serial port can support both most significant bit

(MSB) first and least significant bit (LSB) first data formats.

Figure 35 illustrates how the serial port words are formed for

the MSB first and LSB first modes. The bit order is controlled

by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0,

MSB first. When the LSB first bit is set high, the serial port

interprets both instruction and data bytes LSB first.

SCLK

SDATA

SCLK

SDATA

R/W

A3 A2

A1 A2

D71

D01 D11

D6N D7N

D61

D1N D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

Figure 35. SPI Timing, MSB First (Upper) and LSB First (Lower)

Figure 36 illustrates the timing requirements for a write operation

to the SPI port. After the serial port enable (CS) signal goes low,

data (SDIO) pertaining to the instruction header is read on the

rising edges of the clock (SCLK). To initiate a write operation,

the read/not-write bit is set low. After the instruction header is

read, the eight data bits pertaining to the specified register are

shifted into the SDIO pin on the rising edge of the next eight

clock cycles.

Figure 37 illustrates the timing for a 3-wire read operation to

the SPI port. After CS goes low, data (SDIO) pertaining to the

instruction header is read on the rising edges of SCLK. A read

operation occurs if the read/not-write indicator is set high. After

the address bits of the instruction header are read, the eight data

bits pertaining to the specified register are shifted out of the SDIO

pin on the falling edges of the next eight clock cycles.

Figure 38 illustrates the timing for a 4-wire read operation to

the SPI port. The timing is similar to the 3-wire read operation

with the exception that data appears at the SDO pin only, while the

SDIO pin remains at high impedance throughout the operation.

The SDO pin is an active output only during the data transfer

phase and remains three-stated at all other times.

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

Figure 36. SPI Write Operation Timing

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

Figure 37. SPI 3-Wire Read Operation Timing

SCLK

SDIO

fSCLK

tLOW

tHI

tDS

tDH

R/W

tEZ

tDV

D6 D1

SDO

tEZ

Figure 38. SPI 4-Wire Read Operation Timing

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