AD9739-R2-EBZ datasheet(3/50 Pages) AD

3 / 50 page

Data Sheet

AD9739

Rev. E | Page 3 of 50

REVISION HISTORY

6/2018—Rev. D to Rev. E

Changes to Table 7 ..........................................................................11

Data Receiver Operation at Lower Clock Rates Section ............32

5/2017—Rev. C to Rev. D

Changes to Table 32 ........................................................................48

2/2015—Rev. B to Rev. C

Moved Revision History...................................................................3

Changes to Figure 6.........................................................................11

Changes to Table 19 ........................................................................25

Changes to Theory of Operation Section ....................................28

Changes to Figure 52 ......................................................................36

Changes to Clock Input Considerations Section ........................40

Deleted Figure 60 ............................................................................40

Changes to Table 32 ........................................................................48

1/2012—Rev. A to Rev. B

Changes to Features Section, Applications Section, General

Description Section, Figure 1, Product Highlights Section.........1

Changes to DC Specifications Section ...........................................4

Changed Digital Specifications Section to LVDS Digital

Specifications Section .......................................................................5

Changes to LVDS Digital Specifications Section ..........................5

Added Serial Port Specifications Section and Table 3;

Renumbered Sequentially ................................................................6

Changes to AC Specifications Section............................................7

Changes to Table 5 ............................................................................8

Changes to Table 7 ..........................................................................10

Deleted Static Linearity Section and Figure 7 to Figure 17;

Renumbered Sequentially ..............................................................11

Changed Dynamic Performance Normal Mode, 20 mA Full

Scale (Unless Otherwise Noted) Section to AC (Normal Mode)

Section ..............................................................................................12

Changes to AC (Normal Mode) Section ......................................12

Changed Dynamic Performance Mix Mode, 20 mA Full Scale

Section to AC (Mix Mode) Section...............................................15

Changes to AC (Mix Mode) Section.............................................15

Added Serial Port Interface (SPI) Register Section, SPI Register

Map Description Section, Reset Section, Table 8, and SPI

Operation Section and Figure 34 ..................................................18

Deleted DOCSIS Performance Section and Figure 46 to

Figure 72 and added Figure 35 through Figure 38; Renumbered

Sequentially ................................................................................................. 19

Changes to SPI Register Map Section and Table 9......................20

Added SPI Port Configuration and Software Reset Section,

Power-Down LVDS Interface and TxDAC® Section, Controller

Clock Disable Section, Interrupt Request (IRQ) Enable/Status

Section, and Table 10 to Table 13 ..................................................22

Added TxDAC Full-Scale Current Setting (I

OUTFS) and Sleep

Section, TxDAC Quad-Switch Mode of Operation Section, DCI

Phase Alignment Status Section, SYNC_IN Phase Alignment

Status Section, Data Receiver Controller Configuration Section,

and Table 14 to Table 18 .................................................................23

Added Data Receiver Controller_Data Sample Delay Value

Section, Data and Sync Receiver Controller_DCI Delay

Value/Window and Phase Rotation Section, Data Receiver

Controller_Delay Line Status and Sync Controller SYNC_OUT

Status Section, and Table 19 to Table 21 ......................................24

Deleted Serial Peripheral Interface Section, General Operation

of the Serial Interface Section, Instruction Mode (8-Bit Instruction)

Section, and Serial Interface Port Pin Description Section.......25

Added Sync and Data Receiver Controller Lock/Tracking Status

Section, CLK Input Common Mode Section, Mu Controller

Configuration and Status Section, and Table 22 to Table 24.....25

Deleted MSB/LSB Transfers Section, Serial Port Configuration

Section, and Figure 74 to Figure 79 ..............................................26

Added Part ID Section and Table 25 ............................................26

Changes to Theory of Operation Section ....................................27

Added Figure 39 ..............................................................................27

Deleted SPI Registers Section and Table 8 to Table 31...............28

Moved and Changes to LVDS Data Port Interface Section .......28

Added Figure 40 and Figure 41 .....................................................28

Changes to Figure 42 ......................................................................29

Moved and Changes to Figure 43 .................................................29

Added Data Receiver Controller Initialization Description

Section, Table 26, and Data Receiver Operation at Lower Clock

Rates Section....................................................................................30

Added LVDS Driver and Receiver Input Section, Figure 44 to

Figure 47, and Table 27...................................................................31

Changed and Moved Mu Delay Controller Section to Mu

Controller Section ...........................................................................32

Changes to Mu Controller Section, Figure 48, and Figure 49...32

Added Figure 50 and Table 28.......................................................32

Added Mu Controller Initialization Description Section..........33

Changes to Interrupt Requests Section ........................................34

Added Table 29 ................................................................................34

Changed Synchronization Controller Section to Multiple

Device Synchronization Section ...................................................35

Added Figure 52 ..............................................................................35

Changes to Figure 53 ......................................................................36

Added Sync Controller Initialization Description Section .......36

Added Synchronization Limitations Section...............................37

Changed Applications Information to Analog Interface

Considerations Section...................................................................38

Changes to Analog Modes of Operation Section .......................38

Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39

Added Clock Input Considerations Section, Figure 58 to

Figure 60...........................................................................................39

Deleted Clock Phase Noise Affects on AC Performance Section,

Table 32 to Table 34, Applying Data to the AD9739 Section, and

Figure 87...........................................................................................40

Moved Figure 61..............................................................................40

Changes to Voltage References Section and Analog Outputs

Section ..............................................................................................40

Added Equivalent DAC Output and Transfer Function and

Figure 63...........................................................................................40

AD9739-R2-EBZ 数据表(PDF) 3 Page - Analog Devices

AD9739-R2-EBZ 数据表(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载