AD9739-R2-EBZ datasheet(32/50 Pages) AD

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AD9739

Data Sheet

Rev. E | Page 32 of 50

Set FINE_DEL_SKEW to 2 for a larger DCI sampling

window (Register 0x13 = 0x72). Note that the default

DCI_DEL and SMP_DEL settings of 167 are optimum.

Disable the controller before enabling (that is, Register

0x10 = 0x00).

Enable the Rx controller in two steps: Register 0x10 = 0x02

followed by Register 0x10 = 0x03.

Wait 135K clock cycles.

Read back Register 0x21 and confirm that it is equal to

0x05 to ensure that the DLL loop is locked and tracking.

Include this step for operation <1.6 GSPS. Read back the

DCI_DEL value to determine whether the value falls

within a user-defined tracking guard band. If it does not,

rotate CLKDIVPH by 1 (Register 0x14, Bits[7:6] and go

back to Step 2.

Once the controller is enabled during the initial SPI boot

process (see Table 31 and Table 32), the controller enters a

search mode where it seeks to find the closest rising edge of the

DCI clock (relative to a delayed version of an internal f

DAC/4 clock)

by simultaneously adjusting the delays in the clocks used to

above and below the initial DCI_DEL value. The state machine

first searches for the first rising edge above the DCI_DEL and

then searches for the first rising edge below the DCI_DEL value.

The state machine selects the closest rising edge and then enters

track mode. It is recommended that the default midscale delay

setting (that is, Decimal 167) for the DCI_DEL and SMP_DEL

bits be kept to ensure that the selected edge remains closest to

the delay line midpoint, thus providing the greatest range for

tracking timing variations and preventing the controller from

falling out of lock.

The adjustable delay span for these internal clocks (that is, DCI

and sample delay) is nominally 4 ns. The 10-bit delay value is

user programmable from the decimal equivalent code (0 to 384)

with approximately 12 ps/LSB resolution via the DCI_DEL and

SMP_DEL registers (via Register 0x11 thru Register 0x14). When

the controller is enabled, it overwrites these registers with the

delay value it converges upon. The minimum difference

between this delay value and the minimum/maximum values

(that is, 0 and 334) represents the guard band for tracking.

Therefore, if the controller initially converges upon a DCI_DEL

and SMP_DEL value between 80 and 304, the controller has a

guard band of at least 80 code (approximately 1 ns) to track

phase variations between the clock domains.

Upon initialization of the AD9739, a certain period of time is

required for the data receiver controller to lock onto the DCI clock

signal. Note that, due to its dependency on the mu controller and

synchronization controller (optional), the data receiver controller

should be enabled only after these other controllers have been

enabled and established locked. All of the internal controllers

operate at submultiples of the DAC update rate. The number of

DAC clock cycles required to lock onto the DCI clock is dependent

on whether the synchronization controller is enabled as shown

in Table 26.

Table 26. Typical/Worst-Case Lock Times for LVDS Controller

(Relative to 1/f

DAC)

Synchronization Controller

Typical

Worst Case

Off

70K

135K

Slave

70K

135K

Master

300K

560K

During the SPI initialization process, the user has the option of

polling Register 0x21 (Bit 0, Bit 1, and Bit 3) to determine if the

data receiver controller is locked, has lost lock, or has entered into

track mode before completing the boot sequence. Alternatively, the

appropriate IRQ bit (Register 0x03 and Register 0x04) can be

enabled such that an IRQ output signal is generated upon the

controller establishing lock (see the Interrupt Requests section).

The data receiver controller can also be configured to generate

an interrupt request (IRQ) upon losing lock. Losing lock can be

caused by excessive jitter on the DCI input signal, disruption of

the main DAC clock input, or loss of a power supply rail. To service

the interrupt, the host can poll the RCVR_LCK bit (Register 0x21,

Bit 0) to determine the current state of the controller. If this bit

is cleared, the search/track procedure can be restarted by setting

the RCVR_LOOP_ON bit in Register 0x10, Bit 1. After waiting

the required lock time, the host can poll the RCVR_LCK bit to

see if it has been set. Before leaving the interrupt routine, the

RCVR_FLG_RST bit (Register 0x10, Bit 2) should be reset by

writing a high followed by a low.

Data Receiver Operation at Lower Clock Rates

At clock rates below 1.6 GSPS, it is recommended to include

provisions to rotate the CLKDIVPH setting in the SPI boot

process. As previously mentioned, the delay line can be varied

over a nominal 4 ns window. If the minimum specified clock

rate of 800 MSPS is considered, a DCI clock rate of 200 MSPS

corresponds to a 5 ns period, thus exceeding the delay line length.

Therefore, it becomes possible that the initial startup phase from

the divide-by-4 circuit (and DCO output) is such that the data

receiver controller can never establish initial lock upon power

up.

If the clock rate is increased to 1600 MSPS (that is, DCI clock

period of 2.5 ns), the controller always finds at least two DCI

clock edges, therefore, establishing lock. However, should the

DCI edges fall symmetrically (equal distance) from the initial

DCI_DEL midscale setting, a guard band of ±0.75 ns (that is,

(4.0 − 2.5)/2) results. Rotating the CLKDIVPH can result in an

improvement in this case by skewing one of the DCI edges

toward the DCI_DEL midscale value.

Rotating the CLKDIVPH phase provides a means of adjusting

the delay in course steps of f

DAC/4. For example, in the 800 MSPS

and 1600 MSPS cases described above, rotating the CLKDIVPH

setting by 1 corresponds to a delay shift of 5 ns and 2.5 ns,

respectively. By adding an additional step in the SPI initialization

routine for the data receiver controller, it becomes possible to

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