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AR8327-AL1A-R 数据表(PDF) 82 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R 数据表(HTML) 82 Page - List of Unclassifed Manufacturers |
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82 / 394 page ![]() 82 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 82 • June 2011 COMPANY CONFIDENTIAL 3.2.31 HEADER_CTRL Address 0x0098 SFT&HW RST Table 3-34 summarizes the HEADER_CTRL Register. 3.2.32 PORT0_HEADER_CTRL Address 0x009C SFT&HW RST Table 3-35 summarizes the PORT0_HEADER_CTRL Register. 2 R/W 0 TXMAC_EN_6 Txmac Enable. 1:0 R/W 0 SPEED_6 Speed mode. 2'b00: 10M 2'b01: 100M 2'b10: 1000M 2'b11: error speed mode Table 3-33. Port 6 Status Register Bit R/W Inital Value Mnemonic Description Table 3-34. Header Control Register Bit R/W Inital Value Mnemonic Description 31:17 R/O 0 RESERVED 16 R/W 0 HEADER_LENGTH_SEL 0x1: 4 bytes header 0x0: 2 bytes header 15:0 R/W 0 HEADER_TYPE_VALUE 2 bytes header type added between SA & header field Table 3-35. PORT 0 Header Control Register Bit R/W Inital Value Mnemonic Description 31:6 R/O 0 RESERVED 5 R/W 0 IPG_DEC_EN_0 1'b1: mac will decrease two bytes of IPG when send out frame and receive check. 1'b0: normal IPG 96 bit time 4 R/W 0 MAC_LOOP_BACK_0 1'b1: enable mac loop back at gmii/mii interface |
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