AR8327-AL1A-R datasheet(59/394 Pages) ETC2

59 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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59

3.2.1

MASK_CTRL

Address: 0x0000

HW RST

Table 3-4 summarizes the Mask Control Registers.

NOTE: This register can only be reset by a hardware reset.

3.2.2

PORT0 PAD MODE CTRL

Address: 0x0004

HW RST

Table 3-5 summarizes the PORT0 PAD MODE CTRL Registers

Table 3-4.

Master Control Register

Bit

R/W

Inital

Value

Mnemonic

Description

W/SC

SOFT_RET

1’b1: software reset.

This bit is set by the sofware to initate the

hardware. It should be slef-cleared by the

hardware after the initialization is done.

30:17

R/O

Reserved

R/W

LOAD_EEPROM

load EEPROM enable. This bit is set to

automatically load registers from an EEPROM. It

should be cleared after the loading is complete.

15:8

0x12

DEVICE_ID

Device identifier

7:0

0x02

REV_ID

Revision identifier

Table 3-5.

PORT0 PAD MODE CTRL Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:27

R/O

Reserved

R/W

Mac0_rgmii_en

1'b1 mac0 connected to cpu through RGMII

interface

R/W

Mac0_rgmii_txclk_delay_en

1'b1 RGMII interface txclk(input from cpu)

will be delay, delay value depend on

bit23:bit22

R/W

Mac0_rgmii_rxclk_delay_en

1'b1 RGMII interface rxclk will be delay,

1000M: delay 2ns output to cpu

10/100M: delay value depend on

bit21:bit20

23:22

R/W

Mac0_rgmii_txclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII interface

txclk,2'b11 has the max delay

21:20

R/W

Mac0_rgmii_rxclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII interface

rxclk,2'b11 has the max delay

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