AR8327-AL1A-R datasheet(26/394 Pages) ETC2

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26 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

26 • June 2011

COMPANY CONFIDENTIAL

2.4 Header for Read/Write Register.

The AR8327 supports the read/write register through the Atheros Header. The figure is the frame

format of the read/write register command.

2.5 Media Access Controllers (MAC)

The AR8327 integrates seven independent GB Ethernet MACs that perform all functions in the IEEE

802.3 specifications, for example, frame formatting, frame stripping, CRC checking, CSMA/CD,

collision handling, and back-pressure flow control. Each MAC supports 10 Mbps, 100 Mbps, or 1000

Mbps operation in either full-duplex or half-duplex mode

2.6 Port Status Configuration

The AR8327 supports flexible port status configuration on a group or per-port basis. Each port has

status registers that provide information about the port interface. The first port (port 0) MAC behaves

as a PHY to allow a direct connection to an external MAC (e.g. a management CPU or a MAC inside a

router). In this mode, the AR8327 drives interface clocks from a CLK pin at the desired frequency. Only

full-duplex modes are supported and need to match the mode of the link partner's MAC. The second

RGMII interface supports a PHY interface as a WAN port.

2.6.1

Full-Duplex Flow Control

The AR8327 device supports IEEE 802.3x full-duplex flow control, force-mode full-duplex flow

control, and half-duplex backpressure.

If the link partner supports auto-negotiation, the 802.3x full-duplex flow control is auto-negotiated

between the remote node and the AR8327. If the full-duplex flow control is enabled, when the free

buffer space is almost empty, the AR8327 sends out an IEEE 802.3x compliant PAUSE to stop the

remote device from sending more frames.

2.6.2

Half-Duplex Flow Control

Half-duplex flow control regulates the remote station to avoid dropping packets in network

congestion. Back pressure is supported for half-duplex operations. When the free buffer space is

almost empty, the AR8327 device transmits a jam pattern on the port and forces a collision. If the half-

header

command

data

crc

2 byte

8 byte

Data: 0~16byte

4 byte

padding

4 byte

data

Table 2-4.

Command Format for Read/Write Register using Atheros Header

Bit

Name

Description

18:0

ADDR

The starting register address for the read/write command. The address

must be boundary of word address.

23:20

LENGTH

The data length for read/write register. Maximum 16 bytes.

CMD

1'b0: write

1'b1: read

31:29

CHECK_CODE

Must be 3'b101. otherwise the command would be ignored.

63:32

SEQ_NUM

The Sequence number can be checked by CPU.

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