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AR8327-AL1A-R 数据表(PDF) 18 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R 数据表(HTML) 18 Page - List of Unclassifed Manufacturers |
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18 / 394 page  18 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 18 • June 2011 COMPANY CONFIDENTIAL RXD0_1 A55 I/O, PD RGMII receive data or configuration. These are output signals sourced from either PHY4. All the data bits RXD[7:0]_1 are used in GMII mode. The RXD[3:0]_1 are used as data input when operating in RGMII mode. The reference clock for these output signals will be: RXCLK_1 (pin B47): RGMII/MII PHY type interface and GMII MAC type interface. RXD1_1 B48 I/O, PD RXD2_1 B49 I/O, PD RXD3_1 A57 I/O, PU RXDV_1/RXCTR_1 A54 I/O, PU RGMII receive data valid. This is output signal for either or PHY4. TXEN/TXCTR_1 A58 I, PD RGMII transmit enable, this is an input signal for PHY4. TXD0_1 A59 I, PD RGMII transmit data, these are input signals for either PHY4. All the data bits TXD[7:0]_1 are used in GMII mode. The TXD[3:0]_1 are used as data input when operating in RGMII mode. The reference clock for these input signals: GTXCLK_1 (pin B51): RGMII PHY type interface TXD1_1 B52 I, PD TXD2_1 A60 I, PD TXD3_1 B53 I, PD LED LED_LINK10n_0 A79 O, D LED_LINK10n[4:0] Parallel LED output for 10 Base-T link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending upon the power-on strapping setup. The LED behaviour can be configurable, see the LED Control Registers 0x0050 ~ 0x005C. 10n offset is 0x0058 LED_LINK10n_1 B70 O, D LED_LINK10n_2 A82 O, D LED_LINK10n_3 A84 O, D LED_LINK10n_4 A49 O, D LED_LINK100n_0 B69 O, D LED_LINK100n[4:0] Parallel LED output for 100 Base-T link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending on the power-on strapping. The LED behaviour can be configured, see the LED Control Registers 0x0050 ~ 0x005C. 100n offset is 0x0054 LED_LINK100n_1 A81 O, D LED_LINK100n_2 B72 O, D LED_LINK100n_3 B74 O, D LED_LINK100n_4 B42 O, D LED_LINK1000n_0 A80 O, D LED_LINK1000n[4:0] Parallel LED output for 1000 Base-T link/speed/activity, active low. The LED inactive state can be open-drain or driving high output, depending upon the power-on strapping setup. The LED behaviour can be configured, see the LED Control Registers 0x0050 ~ 0x005C. 1000n offset is 0x0050 LED_LINK1000n_1 B71 O, D LED_LINK1000n_2 A83 O, D LED_LINK1000n_3 A85 O, D LED_LINK1000n_4 A50 O, D UART/MDIO and SPI EEPROM SPI_CLK B45 I/O, PD SPI Clock or configuration SPI_CS A52 I/O, PD SPI Chip select configuration SPI_DI A51 I, PD SPI Data input SPI_DO B44 I/O, PU SPI Data out or configuration UART_RXD/MDC B55 I, PU Management data clock reference UART_TXD/MDIO A62 I/O Management data Serdes Interface SOP B66 OA Serdes differential output pair Table 1-1. Signal to Pin Relationships and Descriptions (continued) Symbol Pin Type Description |
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