AR8327-AL1A-R datasheet(17/394 Pages) ETC2

17 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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17

CH4_TRXN0

A40

IA, OA

Media-dependent interface, MDI[3:0]: Transmitter output

positive/negative

Connect directly to XFMR without any pull-down terminators,

such as resistors or capacitors, required.

CH4_TRXP0

B35

CH4_TRXN1

B37

IA, OA

CH4_TRXP1

A41

CH4_TRXN2

B39

IA, OA

CH4_TRXP2

B38

CH4_TRXN3

A48

IA, OA

CH4_TRXP3

B40

MAC 0/CPU port GMII/RGMII interface

GTXCLK_0/TXCLK_0

A73

I/O, PU

RGMII transmit clock, 125 MHz/25 MHz, or configurable. This

is the reference clock input for RGMII mode, PHY type

interface, or MII mode MAC type interface. It also supports

50MHz clock input (Turbo-MII) when operating in MII mode,

MAC type interface.

RXCLK_0

A65

I/O, PD

RGMII receive clock. This is output clock from MAC0 when

AR8327 operates a PHY type interface. It can be 125MHz/

25MHz/2.5MHz —depending upon the operating speed.

RXD0_0

A68

I/O, PD

RGMII/MII — receive data or configuration; recommend

adding a 22 damping resistor. these are output signals from

MAC0. The RXD[3:0]_0 are used as data input when operating

at RGMII or MII mode. The reference clock for these output

signals will be:

RXCLK_0 (pin A65): RGMII/MII PHY type interface and

GMII-MAC type interface.

RXD1_0

A69

I/O, PD

RXD2_0

A70

I/O, PD

RXD3_0

B60

I/O, PD

RXDV_0/RXCTR_0

A64

I/O, PD

RGMII/MII received data; valid. This is output signal for

MAC0.

TXEN/TXCTR_0

A72

I, PD

RGMII/MII transmit enable, this is input signal for the MAC0.

TXD0_0

B63

I, PD

RGMII/MII transmit data, these are input signals for MAC0.

All the data bits TXD[7:0]_0 are used in GMII mode. The

TXD[3:0]_0 are used as data input when operating on RGMII

or MII mode. The reference clock for these input signals will be:

1. GTXCLK_0 (pin A73): RGMII/MII mode

2. GTXCLK_0 (pin B51): GMII mode

TXD1_0

A74

I, PD

TXD2_0

B64

I, PD

TXD3_0

A75

I, PD

MAC 6/PHY 4 RGMII/MII

GTXCLK_1/TXCLK_1

B51

I/O, PD

RGMII transmit clock, 125 MHz/25 MHz, or configuration.

This is the reference clock input for RGMII mode PHY type

interface or MII mode MAC type interface.

RXCLK_1

B47

I/O, PD

RGMII receive clock. This is output clock from PHY 4 when the

AR8327 operates a PHY type interface. It can be 125MHz/

25MHz/2.5MHz depending on the operating speed.

Table 1-1.

Signal to Pin Relationships and Descriptions (continued)

Symbol

Type

Description

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