AR8327-AL1A-R datasheet(45/394 Pages) ETC2

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Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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2.13 Quality of Service (QoS)

The AR8327 supports six queues (MAC0, MAC5, and MAC6) or four queues (MAC1 ~ MAC4). This

egress queue schedule mechanism can be configured to one of the following modes:

The AR8327 recognizes the QoS information of ingress frames and map to different egress priority

levels. The AR8327 determines the priority of the frames based on DA, TOS/TC, VLAN, and port.

Each has an enable bit that can be applied. When more than one type of priority is selected, the order

in which the frame priority should be applied can be determined. Priority enable bits and select order

bits are set on a by port basis at the port’s base address.

When more than one priority enable bit is set to 1’b1. (DA_PRI_SEL, IP_PRI_SEL, VLAN_PRI_SEL)

can determine the order in which the frame priority should be applied. If *_PRI_SEL is set to 2’b0,

frame priority is determined by that first. Otherwise, priority is determined by which *_PRI_SEL is set

to 2’b01, then 2’b10, 2’b11, etc.

TxSingleCol

32bit

0x98

Total number of successfully transmitted frames that experienced

exactly one collision

TxExcDefer

32bit

0x9C

The number of frames that deferred for an excessive period of time

TxDefer

32bit

0xA0

Total frames whose transmission was delayed on its first attempt

because the medium way was busy

TXLateCol

32bit

0xA4

Total number of times a collision is detected later than 512 bit-times

into the transmission of a frame

Table 2-31.

Mode

Description

Strict Priority (SP)

Any packets residing in the higher priority queues transmit first. Lower priority

packets transmit once these queues are emptied.

Weighted Fair Queuing Each queue is assigned a weight that determines how many packets are sent from each

priority queue.

Mix Mode

The highest one or two priority queues use SP and other queues conform to WRR

Priority

Determined

Description

Set DA_PRI_EN bit [18] to 1’b1 and add the address to the ARL table-set priority_over_en

to 1’b1. ARL priority bits [59:58] can be used as DA priority.

TOS/TC

Set IP_PRI_EN bit [16] to 1’b1, and set the IP priority mapping register 

(0x60–0x6C).

VLAN

Set VLAN_PRI_EN (bit [17]) to 1’b1, and set the TAG priority mapping register (0x70).

Table 2-30.

MIB Counters (continued)

Counter

Width

Offset

Description

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