AR8327-AL1A-R datasheet(11/394 Pages) ETC2

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Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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Revision History

Table 0-1.

AR8161-A Revision History

Date

Revision Details

Revision

2011/2/24

First draft

0.31

2011/6/10

General

n Typo and grammar corrections

n Reference corrections

Pin Description

n Update drawing to re-organize inner(B) and outer (A) pins

n Table 1-1: change A54 pin type to I/O, PU

Function Descriptions

n Table 2-34 and 2-35: change PRIVATE_IP_ADDR_MODE to

PRIVATE_IP_BASE_SEL

n 2.7.2 Action Definition: add description

n 2.21 Memory Map: update memory map

Registers

n 3.2.2 PORT0 PAD MODE CTRL, update bit[18] bit[19] definitions

n 3.2.3 PORT5 PAD MODE CTRL (0x0008): add description for bit[10]

n 3.2.5 PWS_REG (0x0010): update bit definitions

n 3.5.22 to 3.5.24 IPv6 Private Base Address Register 0-2: new registers

n 3.8.12 to 3.8.14 Router Default VID Register 0-2: new registers

n 3.8.16 Router Egress VLAN Mode (0x0C80): new register

n 3.10.24 Debug Port 2 (0xIE): change decimal address to “0d30“

n 3.10.25 Debug Register—Analog Test Control (0x00): new register

n 3.10.26 Debug Register—System Mode Control (0x03): new register

n 3.10.28 Debug Register—Hib Control and Auto Negotiation Test Register

(0x0B): new register

n 3.10.30 Debug Register—Green Feature Configure Register (0x3D): new

n 3.13 MMD7—Auto-negotiation Register: update bit definitions

n 3.13.3 to 3.13.7: update decimal address

n 4.6 Typical Power Consumption Parameters: update “two ports active” and

“three ports active“ values

Package Dimensions

n Update package illustration

Ordering

n Update ordering method for tape&reel and tray

Top Side Marking

n Add package top marking illustration

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