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AR8327-AL1A-R 数据表(PDF) 66 Page - List of Unclassifed Manufacturers

部件名 AR8327-AL1A-R
功能描述  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

AR8327-AL1A-R 数据表(HTML) 66 Page - List of Unclassifed Manufacturers

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66 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch
Atheros Communications, Inc.
66 • June 2011
COMPANY CONFIDENTIAL
Table 3-10 summarizes the GLOBAL_INT1Register 1.
3.2.8
GLOBAL_INT0
Address 0x0028
SFT&HW RST
Table 3-11 summarizes the GLOBAL_INT0 Register 0
Table 3-10.
Global Interrupt Register 1
Bit
R/W
Inital
Value
Mnemonic
Description
31:24
R/O
0
RESERVED
23:19
R/O
0
RESERVED
18
R/W1C
0
EEPROM_ERR_INT
Interrupt when error occur during load
eeprom.
17
R/W1C
0
EEPROM_INT
Interrupt when EEPROM load done.
16
R/W1C
0
MDIO_DONE_INT
MDIO access switch register done
interrupt
15
R/W1C
0
PHY_INT
Physical layer interrupt.
14
R/W1C
0
QM_ERR_INT
Interrupt when qm detect error.
13
R/W1C
0
LOOKUP_ERR_INT
Interrupt when lookup detect error.
12
R/W1C
0
LOOP_CHECK_INT
Interrupt when loop checked by
hardware
11:1
R/O
0
RESERVED
0
R/W
0
BIST_DONE_INT
Interrupt when BIST done
Table 3-11.
Global Interrupt Mask Register 0
Bit
R/W
Inital
Value
Mnemonic
Description
31:30
R/O
0
RESERVED
29
R/W
0
ACL_INI_INT_EN
Enable Interrupt when ACL memory
initial done
28
R/W
0
LOOKUP_INI_INT_EN
Enable Interrupt when address table
initial done.(including ARL, Reserved
ARL, VLAN)
27
R/W
0
QM_INI_INT_EN
Enable Interrupt when qm memory
initial done
26
R/W
0
MIB_INI_INT_EN
Enable Interrupt when mib memory
initial done
25
R/W
0
OFFLOAD_INI_INT_EN
Enable Interrupt when OFFLOAD
memory initial done.
24
R/W
0
HARDWARE_INI_DONE_EN
Enable Interrupt when hardware
memory initial done
23
R/W
0
ACL_MATCH_INT_EN
Enable Interrupt when acl match



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