AR8327-AL1A-R datasheet(89/394 Pages) ETC2

89 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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3.3 EEE CTRL REGISTER SUMMARY (Address Range 0x0100 ~ 0x0168)

Table 3-43 summarizes the EEE control registers.

3.3.1

EEE_CTRL

Address 0x0100

SFT&HW RST

Table 3-44 summarizes the EEE_CTRL Register.

Table 3-43.

EEE Control Register Summary

Name

Address

Reset

EEE CONTROL REGISTER

0x0100

HARD AND SOFT

PORT1 EEE VARIABLE REGISTER

0x0120~0x0128

HARD AND SOFT

PORT2 EEE VARIABLE REGISTER

0x0130~0x0018

HARD AND SOFT

PORT3 EEE VARIABLE REGISTER

0x0140~0x0148

HARD AND SOFT

PORT4 EEE VARIABLE REGISTER

0x0150~0x0158

HARD AND SOFT

PORT5 EEE VARIABLE REGISTER

0x0160~0x0168

HARD AND SOFT

Table 3-44.

EEE Control Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:14

R/O

RESERVED

R/W

RESERVED

R/W

LPI_EN_5

LPI enable for PORT5

R/W

RESERVED

R/W

LPI_EN_4

LPI enable for PORT4

R/W

RESERVED

R/W

LPI_EN_3

LPI enable for PORT3

R/W

RESERVED

R/W

LPI_EN_2

LPI enable for PORT2

R/W

RESERVED

R/W

LPI_EN_1

LPI enable for PORT1,

1: disable PHY sleep

0: enable PHY sleep

R/W

EEE_CPU_CHANGE_EN

1: CPU can set the resolved value

R/W

EEE_LLDP_TO_CPU_EN

1’b1: EEE LLDP packet to CPU

1’b0: EEE LLDP packet to deheader

R/W

EEE_EN

1: support LLDP autonegation PHY wake-up

time

R/O

RESERVED

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