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AR8327-AL1A-R 数据表(PDF) 87 Page - List of Unclassifed Manufacturers

部件名 AR8327-AL1A-R
功能描述  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

AR8327-AL1A-R 数据表(HTML) 87 Page - List of Unclassifed Manufacturers

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Atheros Communications, Inc.
AR8327/AR8327N Seven-port Gigabit Ethernet
Switch
87
Table 3-42 summarizes the SGMII_CTRL Register.
Table 3-42.
SGMII Control Register
Bit
R/W
Inital
Value
Mnemonic
Description
31
R/W
1
full_duplex_25m
Full_duplex in the base-page of base-x for Auto-
Negotiation.
30
R/W
1
half_duplex_25m
half_duplex in the base-page of base-x for Auto-
Negotiation.
29:28
R/W
00
Remote_fault_25m
Remote_fault[1:0] in the base-page of base-x for
Auto-Negotiation. Generated by the remote_fault
logic internal MAC.
27
R/W
0
Next_page_25m
Next_page index in the base-page of base-x and
SGMII PHY/MAC for Auto-Negotiation.
26
R/W
1
pause_25m
pause in the base-page of base-x and SGMII-PHY/
MAC for Auto-Negotiation. This part is not
included in the standard for SGMII.
25
R/W
1
asym_pause_25m
asym_pause in the base-page of base-x and SGMII-
PHY/MAC for Auto-Negotiation. This part is not
included in the standard for SGMII.
24
R/W
1
Pause_sg_tx_en_25m
Enable transmitting pause in the base-page of base-
x and SGMII-PHY/MAC for Auto-Negotiation.
23:22
R/W
0
mode_ctrl_25m
Mode_ctrl signal for mode selection among BASE-
X(2'h0), SGMII-PHY(2'h1), .and SGMII-MAC(2'h2).
21
R/W
0
Mr_loopback,
force_speed
Indicate loopback from MII register of cooper PHY.
And Force speed control signal.
20
R/W
0
mr_reg4_ch_25m
Indicate register 4 has changed.
19
R/W
0
auto_lpi_25m
When rx_lpi_active active for once, the register will
latch this to indicate that the link-partner.
18
R/W
0
Prbs_en
Enable serdes prbs test function.
17
R/W
0
Sgmii_th_los[1]
Combined with bit15,
Signal detection threshold setting control
00, default; 01, -2dB; 10/11, +2dB
16
R/W
0
Dis_auto_lpi_25m
Disable the auto-detect link-partner's az ability.
15
R/W
0
Sgmii_th_los[0]
Same as bit17
14:13
R/W
11
sgmii_cdr_bw
CDR digital accumulator length control
00: +/-0, 01 : +/-2, 10: +/-4, 11: +/-8
12:10
R/W
3’b001
sgmii_txdr_ctrl
Default = 001
000, driver output Vdiff,pp=500mv
001, 600mv; 010, 700mv; 011, 800mv; 100, 900mv;
101, 1v; 110, 1.1v; 111, 1.2v
9:8
R/W
0
sgmii_fiber_mode
00, not in fiber mode
01, Reserved
10, Reserved
11, 1000Base-FX mode
7
R/W
1
sgmii_sel_clk125m
0, sgmii_clk125m_rx_delay is not delayed
1, sgmii_clk125m_rx_delay is delayed by 2ns



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