AR8327-AL1A-R datasheet(62/394 Pages) ETC2

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62 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

62 • June 2011

COMPANY CONFIDENTIAL

Table 3-7 summarizes the PORT6 PAD MODE CTRL Registers.

Table 3-7.

PORT6 PAD MODE CTRL Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:27

R/O

Reserved

R/W

Mac6_rgmii_en

1'b1 mac6 connected to cpu through

RGMII interface

R/W

Mac6_rgmii_txclk_delay_en

1'b1 RGMII interface txclk(input from

cpu) will be delay, delay value depend

on bit23:bit22

R/W

Mac6_rgmii_rxclk_delay_en

1'b1 RGMII interface rxclk delay.

1000M: delay 2ns output to cpu

10/100M: delay value depend on

bit21:bit20

23:22

R/W

Mac6_rgmii_txclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII

interface txclk,2'b11 has the max delay

21:20

R/W

Mac6_rgmii_rxclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII

interface rxclk,2'b11 has the max delay

R/O

RESERVED

R/O

Phy4_mii_en

1'b1 phy4 connected to cpu through

MII interface

R/O

Phy4_rgmii_en

1'b1 phy4 connected to cpu through

RMII interface

R/O

Phy4_gmii_en

1'b1 phy4 connected to cpu through

GMII interface

R/O

RESERVED

R/W

Mac6_phy_gmii_en

1'b1 mac6 connected to cpu through

GMII interface, phy mode

R/W

Mac6_phy_gmii_txclk_sel

1'b1 select invert clock input for port6

phymode, GMII interface txclk

R/W

Mac6_phy_gmii_rxclk_sel

1'b1 select invert clock output for port6

phymode or PHY 4, GMII interface

rxclk

R/W

Mac6_phy_mii_pipe_rxclk_sel

1'b1 select clock edge for rxpipe,default

is invert

R/W

Mac6_phy_mii_en

1'b1 mac6 connected to cpu through

MII interface, phy mode

R/W

Mac6_phy_mii_txclk_sel

1'b1 select invert clock output for port6

phymode ,MII interface txclk

R/W

Mac6_phy_mii_rxclk_sel

1'b1 select invert clock output for port6

phymode ,MII interface rxclk

R/W

Mac6_sgmii_en

R/W

Mac6_mac_gmii_en

1'b1 mac6 connected to cpu through

GMII interface, mac mode

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