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AR8327-AL1A-R 数据表(PDF) 369 Page - List of Unclassifed Manufacturers

部件名 AR8327-AL1A-R
功能描述  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

AR8327-AL1A-R 数据表(HTML) 369 Page - List of Unclassifed Manufacturers

Back Button AR8327-AL1A-R Datasheet HTML 365Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 366Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 367Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 368Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 369Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 370Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 371Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 372Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 373Page - List of Unclassifed Manufacturers Next Button
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Atheros Communications, Inc.
AR8327/AR8327N Seven-port Gigabit Ethernet
Switch
•
369
3.10.27 Debug Register — System Mode
Control
Address Offset: 0x05, or 0d05
Table 3-392, “Debug Register — System Control Mode,” on page 369 summarizes the Register
Table 3-392.
Debug Register — System Control Mode
4:3
RESERVED
Mode
R/W
Reserved
HW Rst
2’h1
SW Rst
Retain
2
MANU_SWITC
H_ON
Mode
R/W
DAC amplitude adjustment
1 = add +6%
0 = no increase
HW Rst
1
SW Rst
Retain
1
RES
Mode
R/W
Reserved
HW Rst
1
SW Rst
Retain
0
RES
Mode
R/W
Reserved
HW Rst
0
SW Rst
Retain
Table 3-391.
Debug Register — System Mode Control
Bit
Symbol
Type
Description
Bit
Symbol
Type
Description
15
RES
Mode
RO
Reserved
HW Rst
0
SW Rst
0
14
RES
Mode
RO
Reserved
HW Rst
0
SW Rst
0
13
RES
Mode
R/W
Reserved
HW Rst
1
SW Rst
Retain
12
RES
Mode
R/W
Reserved
HW Rst
1
SW Rst
Retain
11
RES
Mode
R/W
Reserved
HW Rst
1
SW Rst
Retain



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