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DS31256 数据表(PDF) 59 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 59 Page - Maxim Integrated Products |
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59 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 59 of 183 Figure 6-6. Receive V.54 State Machine VRST = 1 VLB = 0 VTO = 0 SLBP = 0 Search for Loop Up Pattern for 32 VCLKs Reset 4 second timer; wait for Loss of Sync or All 1s (64 in a Row) or for the 4 second timer to expire Search for Loop Down Pattern VLB = 1 Sync = 0 VLB = 0 Sync = 1 VTO = 1 Sync = 0 Sync = 0 or 4 Second Timer Has Expired Sync = 1 All Ones Time Out (VTO) Loopback (VLB); both in RP[n]CR V.54 State Machine CLK Data VRST (in RP[n]CR) v54sm All Ones SYSCLK Sysclk is used only to time a 4 second timer. It is run into a 2E27 counter which provides a 4.03 second time out with a 33MHz clock and a 5.37 second time out with a 25MHz clock wait for Loss of Sync or All 1s (64 in a Row) Sync = 0 Change of State in Status (SLBP); in SV54 SLBP = 1 SLBP = 1 |
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