| 数据搜索系统,热门电子元器件搜索 |
|
DS31256 数据表(PDF) 47 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
DS31256 数据表(HTML) 47 Page - Maxim Integrated Products |
|
47 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 47 of 183 Figure 6-2. Port Timing (Channelized and Unchannelized Applications) RC[n] / TC[n] Normal Mode RD[n] TD[n] RS[n] / TS[n] 0 Clock Early & Not Inverted RS[n] / TS[n] 1/2 Clock Early & Inverted RS[n] / TS[n] 1 Clock Early & Not Inverted RS[n] / TS[n] 2 Clocks Early & Not Inverted Bit 0 Bit 192 or 255 or 511 or 1023 Bit 1 Bit 191 or 254 or 510 or 1022 First Bit of the Frame Last Bit of the Frame RC[n] / TC[n] Inverted Mode tdm_tim |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |