DS31256 datasheet(7/183 Pages) MAXIM

7 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

7 of 183

Table 1-A. Data Sheet Definitions

The following terms are used throughout this data sheet.

Note: The DS31256’s ports are numbered 0 to 255; the HDLC channels are numbered 1 to 256. HDLC Channel 1 is always associated with

Port 0, HDLC Channel 2 with Port 1, and so on.

TERM

DEFINITION

BERT

Bit Error-Rate Tester

Descriptor

A message passed back and forth between the DMA and the host

Dword

Double word; a 32-bit data entity

DMA

Direct Memory Access

FIFO

First In, First Out. A temporary memory storage scheme.

HDLC

High-Level Data-Link Control

Host

The main controller that resides on the PCI Bus.

n/a

Not assigned

V.54

A pseudorandom pattern that controls loopbacks (see ANSI T1.403)

2. DETAILED DESCRIPTION

This data sheet is broken into sections detailing each of the DS31256’s blocks. See Figure 2-1 for a block

diagram.

The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The

DS31256 can handle up to 60 T1 or 64 E1 data streams or two T3 data streams simultaneously. Each of

the 16 physical ports can handle up to two or four T1 or E1 data streams. Section 17 details a few

common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC

block and grooms data from the HDLC block for transmission. The block can perform both channelized

and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the

host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host

assigns HDLC channels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in

Section 6.3. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and

detect both pseudorandom and repeating bit patterns, and is used to test and stress data communication

links.

The HDLC block consists of two types of HDLC controllers. There are 16 slow HDLC engines (one for

each port) that are capable of operating at speeds up to 8.192Mbps in channelized mode and up to

10Mbps in unchannelized mode. There are also three fast HDLC engines, which only reside on Ports 0,

1, and 2 and they are capable of operating at speeds up to 52Mbps. Via the RP[n]CR and TP[n]CR

registers in the Layer 1 block, the host configures Ports 0, 1, and 2 to use either the slow or the fast

HDLC engine. The HDLC engines perform all of the Layer 2 processing, including zero stuffing and

destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.

In the receive path, the following process occurs. The HDLC engines collect the incoming data into

32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are

priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the

FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC

channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has

no bearing on the priority of this data transfer. This situation is of no real concern however since the

DS31256 数据表(PDF) 7 Page - Maxim Integrated Products

DS31256 数据表(HTML) 7 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载