DS31256 datasheet(40/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

40 of 183

SDMA

Status Register for DMA

0028h

Bit #

Name

RLBRE

RLBR

ROVFL

RLENC

RABRT

RCRCE

n/a

Default

Bit #

Name

TDQWE

TDQW

TPQR

TUDFL

RDQWE

RDQW

RSBRE

RSBR

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE). This status bit is set to 1 if any of the receive HDLC

channels experiences a CRC checksum error. The RCRCE bit is cleared when read and is not set again until

another CRC checksum error has occurred. If enabled through the RCRCE bit in the interrupt mask for SDMA

(ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the

PINTA signal pin and also

at the

LINT if the local bus is in configuration mode.

Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive

HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has

been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit

causes a hardware interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if the local bus is in

configuration mode.

Bit 4/Status Bit for Receive HDLC Length Check (RLENC). This status bit is set to 1 if any of the HDLC

channels:

• exceeds the octet length count (if so enabled to check for octet length)

• receives an HDLC packet that does not meet the minimum length criteria of either 4 or 6 bytes

• experiences a nonintegral number of octets between opening and closing flags

The RLENC bit is cleared when read and is not set again until another length violation has occurred. If enabled

through the RLENC bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware

interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if the local bus is in configuration

mode.

Bit 5/Status Bit for Receive FIFO Overflow (ROVFL). This status bit is set to 1 if any of the HDLC channels

experiences an overflow in the receive FIFO. The ROVFL bit is cleared when read and is not set again until

another overflow has occurred. If enabled through the ROVFL bit in the interrupt mask for SDMA (ISDMA), the

setting of this bit causes a hardware interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if

the local bus is in configuration mode.

Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit is set to 1 each time the receive

DMA completes a single read or a burst read of the large buffer free queue. The RLBR bit is cleared when read

and is not be set again until another read of the large buffer free queue has occurred. If enabled through the RLBR

bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus

through the

PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit is set to 1 each time the

receive DMA tries to read the large buffer free queue and it is empty. The RLBRE bit is cleared when read and is

not set again until another read of the large buffer free queue detects that it is empty. If enabled through the

RLBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI

bus through the

PINTA signal pin and also at the LINT if the local bus is in configuration mode.

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