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DS31256 数据表(PDF) 31 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 31 Page - Maxim Integrated Products |
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31 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 31 of 183 4.11 PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ ADDRESS NAME REGISTER SECTION 0x000/0A00 PVID0 PCI Vendor ID/Device ID 0 10.2 0x004/0A04 PCMD0 PCI Command Status 0 10.2 0x008/0A08 PRCC0 PCI Revision ID/Class Code 0 10.2 0x00C/0A0C PLTH0 PCI Cache Line Size/Latency Timer/Header Type 0 10.2 0x010/0A10 PDCM PCI Device Configuration Memory Base Address 10.2 0x03C/0A3C PINTL0 PCI Interrupt Line and Pin/Min Grant/Max Latency 0 10.2 4.12 PCI Configuration Registers for Function 1 (PIDSEL/Bxx) OFFSET/ ADDRESS NAME REGISTER SECTION 0x100/0B00 PVID1 PCI Vendor ID/Device ID 1 10.2 0x104/0B04 PCMD1 PCI Command Status 1 10.2 0x108/0B08 PRCC1 PCI Revision ID/Class Code 1 10.2 0x10C/0B0C PLTH1 PCI Cache Line Size/Latency Timer/Header Type 1 10.2 0x110/0B10 PLBM PCI Device Local Base Memory Base Address 10.2 0x13C/0B3C PINTL1 PCI Interrupt Line and Pin/Min Grant/Max Latency 1 10.2 |
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