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DS31256 数据表(PDF) 42 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 42 Page - Maxim Integrated Products |
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42 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 42 of 183 Register Name: ISDMA Register Description: Interrupt Mask Register for SDMA Register Address: 002Ch Bit # 7 6 5 4 3 2 1 0 Name RLBRE RLBR ROVFL RLENC RABRT RCRCE n/a n/a Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name TDQWE TDQW TPQR TUDFL RDQWE RDQW RSBRE RSBR Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE) 0 = interrupt masked 1 = interrupt unmasked Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT) 0 = interrupt masked 1 = interrupt unmasked Bit 4/Status Bit for Receive HDLC Length Check (RLENC) 0 = interrupt masked 1 = interrupt unmasked Bit 5/Status Bit for Receive FIFO Overflow (ROVFL) 0 = interrupt masked 1 = interrupt unmasked Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR) 0 = interrupt masked 1 = interrupt unmasked Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE) 0 = interrupt masked 1 = interrupt unmasked Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR) 0 = interrupt masked 1 = interrupt unmasked Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE) 0 = interrupt masked 1 = interrupt unmasked Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW) 0 = interrupt masked 1 = interrupt unmasked Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE) 0 = interrupt masked 1 = interrupt unmasked Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL) 0 = interrupt masked 1 = interrupt unmasked |
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