DS31256 datasheet(54/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted. It is used

by the receive-side Layer 1 state machine when channelized local loopback (CLLB) is enabled.

R[n]CFG[j] where n = 0 to 15 for each port and j = 0 to 127 for each DS0

Receive Layer 1 Configuration Register

Indirect Access through CP[n]RD

Bit #

Name

RCH#(8): Receive HDLC Channel Number

Default

Bit #

Name

RCHEN

RBERT

n/a

RV54

n/a

CLLB

n/a

R56

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/Receive Channel Number (RCH#). The CPU loads the number of the HDLC channels associated

with this particular DS0 channel. If the port is running in an unchannelized mode (RUEN = 1), the HDLC channel

number only needs to be loaded into R[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC

channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is

enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled.

00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0)

00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1)

00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2)

00000011 (03h) = HDLC channel number 4

11111111 (FFh) = HDLC channel number 256

Bit 8/Receive 56kbps (R56). If the port is running a channelized application, this bit determines whether the LSB

of each DS0 should be processed or not. If this bit is set, the LSB of each DS0 channel is not routed to the HDLC

controller (or the BERT, if it has been enabled through the RBERT bit). This bit does not affect the operation of

the V.54 detector. It always searches on all 8 bits in the DS0.

0 = 64kbps (use all 8 bits in the DS0)

1 = 56kbps (use only the first 7 bits received in the DS0)

Bit 10/Channelized Local Loopback Enable (CLLB). Enabling this loopback forces the transmit data to replace

the receive data. This bit must be set for each and every DS0 channel that is to be looped back. In order for the

loopback to become active, the DS0 channel must be enabled (RCHEN = 1) and the DS0 channel must be set into

the 64kbps mode (R56 = 0).

0 = loopback disabled

1 = loopback enabled

Bit 12/Receive V.54 Enable (RV54E). If this bit is cleared, this DS0 channel is not examined to check if the V.54

loop pattern is present. If set, the DS0 is examined for the V.54 loop pattern. When searching for the V.54 pattern

within a DS0 channel, all 8 bits of the DS0 channel are examined, regardless of how the DS0 channel is

configured (i.e., 64k or 56k).

0 = do not examine this DS0 channel for the V.54 loop pattern

1 = examine this DS0 channel for the V.54 loop pattern

Bit 14/Route Data Into BERT (RBERT). Setting this bit routes the DS0 data into the BERT function. If the DS0

channel has been configured for 56kbps operation (R56 = 1), the LSB of each DS0 channel is not routed to the

BERT block. In order for the data to make it to the BERT block, the host must also configure the BERT for the

proper port through the master control register (Section 5).

0 = do not route data to BERT

1 = route data to BERT

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