DS31256 datasheet(70/183 Pages) MAXIM

70 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

70 of 183

zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the

device must not be configured to write done-queue descriptors only at the end of a packet, if it is desired that done-

queue descriptors be written; there is not an end of packet on the receive side in transparent mode by definition.

Please note that an end of packet does not occur on the receive side while in transparent mode.

0 = transparent mode disabled

1 = transparent mode enabled

Bit 1/Receive Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC engine does not

check to see if the octet length of the received packets exceeds the count loaded into the receive HDLC packet

length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the octet length of the received

packets exceeds the count loaded into the RHPL register. When an incoming packet exceeds the maximum length,

the packet is aborted and the remainder is discarded. This bit is ignored if the HDLC channel is set to transparent

mode (RTRANS = 1).

0 = octet length detection disabled

1 = octet length detection enabled

Bits 2, 3/Receive CRC Selection (RCRC0/RCRC1). These two bits are ignored if the HDLC channel is set into

transparent mode (RTRANS = 1).

RCRC1

RCRC0

ACTION

No CRC verification performed

16-bit CRC (CCITT/ITU Q.921)

32-bit CRC

Illegal state

Bit 4/Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not inverted

before processing. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and

FCS) before processing the data. The data is not reinverted before passing to the FIFO.

0 = do not invert data

1 = invert all data (including flags and FCS)

Bit 5/Receive Bit Flip (RBF). When this bit is set low, the HDLC engine places the first HDLC bit received in the

lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the

HDLC controller places the first HDLC bit received in the highest bit position of the PCI bus bytes (i.e., PAD[7],

PAD[15], PAD[23], PAD[31]).

0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI bus

1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI bus

Bit 6/Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through to the PCI

bus. When this bit is set low, the HDLC engine includes the 2-Byte FCS (16-bit) or 4-Byte FCS (32-bit) in the

data that it transfers to the PCI bus. This bit is ignored if the HDLC channel is set into transparent mode

(RTRANS = 1).

0 = send FCS to the PCI bus

1 = do not send the FCS to the PCI bus

Bit 7/Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine examines the incoming data

stream for the abort sequence, which is seven or more consecutive 1s. When this bit is set high, the incoming data

stream is not examined for the abort sequence, and, if an incoming abort sequence is received, no action is taken.

This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1).

Bit 8/Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine zero destuffs the

incoming data stream. When this bit is set high, the HDLC engine does not zero destuff the incoming data stream.

This bit is ignored when the HDLC engine is configured in the transparent mode (RTRANS = 1).

DS31256 数据表(PDF) 70 Page - Maxim Integrated Products

DS31256 数据表(HTML) 70 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载