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DS31256 数据表(PDF) 68 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 68 Page - Maxim Integrated Products |
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68 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 68 of 183 Table 7-B. Receive HDLC Functions FUNCTION DESCRIPTION Zero Destuff This operation is disabled if the channel is set to transparent mode. Flag Detection and Byte Alignment Okay to have two packets separated by only one flag or by two flags sharing a 0. This operation is disabled if the channel is set to transparent mode. Octet Length Check The minimum check is for 4 Bytes with CRC-16 and 6 Bytes with CRC-32 (packets with less than the minimum lengths are not passed to the PCI bus). The maximum check is programmable up to 65,536 Bytes through the RHPL register. The maximum check can be disabled through the ROLD control bit in the RHCD register. The minimum and maximum counts include the FCS. An error is also reported if a noninteger number of octets occur between flags. CRC Check Can be either set to CRC-16 or CRC-32 or none. The CRC can be passed through to the PCI bus or not. The CRC check is disabled if the channel is set to transparent mode. Abort Detection Checks for seven or more 1s in a row. Invert Data All data (including the flags and FCS) is inverted before HDLC processing. Also available in the transparent mode. Bit Flip The first bit received becomes either the LSB (normal mode) or the MSB (telecom mode) of the byte stored in the FIFO. Also available in the transparent mode. Transparent Mode If enabled, flag detection, zero destuffing, abort detection, length checking, and FCS checking are disabled. Data is passed to the PCI bus on octet (i.e., byte) boundaries in channelized operation. Table 7-C. Transmit HDLC Functions Zero Stuffing Only used between opening and closing flags. Is disabled between a closing flag and an opening flag and for sending aborts and/or interfill data. Disabled if the channel is set to the transparent mode. Interfill Selection Can be either 7Eh or FFh. Flag Generation A programmable number of flags (1 to 16) can be set between packets. Disabled if the channel is set to the transparent mode. CRC Generation Can be either CRC-16 or CRC-32 or none. Disabled if the channel is set to transparent mode. Invert Data All data (including the flags and FCS) is inverted after processing. Also available in the transparent mode. Bit Flip The LSB (normal mode) of the byte from the FIFO becomes the first bit sent or the MSB (telecom mode) becomes the first bit sent. Also available in the transparent mode. Transparent Mode If enabled, flag generation, zero stuffing, and FCS generation is disabled. Passes bytes from the PCI Bus to Layer 1 on octet (byte) boundaries. Invert FCS When enabled, it inverts all of the bits in the FCS (useful for HDLC testing). |
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