DS31256 datasheet(33/183 Pages) MAXIM

33 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

33 of 183

Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive

DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is

enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this

bit.

0 = receive DMA is disabled

1 = receive DMA is enabled

Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1). These

two bits select the maximum burst length that the receive DMA is allowed on the PCI bus. The DMA can be

restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256

dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system

environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency

and bus efficiency.

00 = burst length maximum is 32 dwords

01 = burst length maximum is 64 dwords

10 = burst length maximum is 128 dwords

11 = burst length maximum is 256 dwords

Bit 3/Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to 0, the

transmit DMA does not pass any data from the PCI bus to the transmit FIFO, even if one or more HDLC channels

is enabled. On device initialization, the host should fully configure the transmit DMA before enabling it through

this bit.

0 = transmit DMA is disabled

1 = transmit DMA is enabled

Bit 4/Transmit DMA Throttle Select Bit 0 (TDT0); Bit 5/Transmit DMA Throttle Select Bit 1 (TDT1). These

two bits select the maximum burst length the transmit DMA is allowed on the PCI bus. The DMA can be restricted

to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords

(1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment

for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus

efficiency.

00 = burst length maximum is 32 dwords

01 = burst length maximum is 64 dwords

10 = burst length maximum is 128 dwords

11 = burst length maximum is 256 dwords

Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either

Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest

address, while Big Endian places the least significant byte at the highest address. This bit setting only affects

HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI

configuration registers, and local bus are always in Little Endian format.

0 = HDLC packet data on the PCI bus is in Little Endian format

1 = HDLC packet data on the PCI bus is in Big Endian format

DS31256 数据表(PDF) 33 Page - Maxim Integrated Products

DS31256 数据表(HTML) 33 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载