DS31256 datasheet(9/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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which are called “large” and “small” but that can be set to any size up to 8188 bytes. The user has the

option to store the incoming data either, only in the large buffers, only in the small buffers, or fill a small

buffer first and then fill large buffers as needed. The varying buffer storage options allow the user to

make the best use of the available memory and to be able to balance the tradeoff between latency and bus

utilization.

The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to

obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are

handed back and forth from the DMA to the host. Since this descriptor transfer utilizes bus cycles, the

DMA has been structured to minimize the number of transfers required. For example on the receive side,

the DMA obtains descriptors from the host to know where in the 32-bit address space to place the

incoming packet data. These descriptors are known as free-queue descriptors. When the DMA reads

these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where

to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS31256 DMA

does not need to use any more bus cycles to determine where to place the data. Other DMA architectures

tend to use pointers, which require them to go back onto the bus to obtain more information and hence

use more bus cycles.

Another technique that the DMA uses to maximize bus utilization is the ability to burst read and write

the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of

one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read

and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions

which reduces the total number of bus cycles needed.

The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus

cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions that

reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.

The Local Bus block has two modes of operation. It can be used as either a bridge from the PCI Bus in

which case it is a bus master or it can be used as a configuration bus in which case it is a bus slave. The

bridge mode allows the host on the PCI Bus to access the local bus. The DS31256 maps data from the

PCI Bus to the local bus. In the configuration mode, the local bus is used only to control and monitor the

DS31256 while the HDLC packet data will still be transferred to the host through the PCI Bus.

DS31256 数据表(PDF) 9 Page - Maxim Integrated Products