DS31256 datasheet(44/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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6. LAYER 1

6.1 General Description

Figure 6-1 shows the Layer 1 block. Each of the DS31256’s 16 Layer 1 ports can be configured to

support either a channelized application or an unchannelized application. Users can mix the applications

on the ports as needed. Some or all of the ports can be channelized, while the others can be configured as

unchannelized. A channelized application is defined as one that requires an 8kHz synchronization pulse

to subdivide the serial data stream into a set of 8-bit DS0 channels (also called time slots), which are

time division multiplexed (TDM) one after another. Ports running a channelized application require an

8kHz pulse at the RS and TS signals. An unchannelized application is defined as a synchronous clock

and data interface. No synchronization pulse is required and the RS and TS signals are forced low in this

application. Section 17 contains examples of some various configurations.

In channelized applications, the Layer 1 ports can be configured to operate in one of four modes, as

shown in Table 6-A. Each port is capable of handling one, two, or four T1/E1 data streams. When more

than one T1/E1 data stream is applied to the port, the individual T1/E1 data streams must be TDM into a

single data stream at either a 4.096MHz or 8.192MHz data rate. Since the DS31256 can map any HDLC

channel to any DS0 channel, it can support any form (byte interleaved, frame interleaved, etc.) of TDM

that the application may require. On a DS0-by-DS0 basis, the DS31256 can be configured to process all

8 bits (64kbps), the seven most significant bits (56kbps), or no data.

Table 6-A. Channelized Port Modes

MODE

FUNCTION

T1 (1.544MHz)

N x 64kbps or N x 56kbps; where N = 1 to 24 (one T1 data stream)

E1 (2.048MHz)

N x 64kbps or N x 56kbps; where N = 1 to 32 (one T1 or E1 data stream)

4.096MHz

N x 64kbps or N x 56kbps; where N = 1 to 64 (two T1 or E1 data streams)

8.192MHz

N x 64kbps or N x 56kbps; where N = 1 to 128 (four T1 or E1 data streams)

Each port in the Layer 1 block is connected to a slow HDLC engine. The slow HDLC engine can handle

channelized applications at speeds up to 8.192Mbps and unchannelized applications at speeds of up to

10Mbps. Ports 0 and 1 have the added capability of fast HDLC engines that can only handle

unchannelized applications but at speeds of up to 52MHz.

Each port has an associated receive port control register (RP[n]CR, where n = 0 to 15) and a transmit

port control register (TP[n]CR where n = 0 to 15). These control registers are defined in detail in

Section 6.2. They control all the circuitry in the Layer 1 block with the exception of the Layer 1 state

machine, which is shown in the center of the block diagram (Figure 6-1).

Each port contains a Layer 1 state machine that connects directly to the slow HDLC engine. It prepares

the raw incoming data for the slow HDLC engine and grooms the outgoing data. The Layer 1 state

machine performs a number of tasks that include the following:

Assigning the HDLC channel number to the incoming and outgoing data

Channelized local and network loopbacks

Channelized selection of 64kbps, 56kbps, or no data

Channelized transmits DS0 channel fill of all ones

Routing data to and from the BERT function

Routing data to the V.54 loop pattern detector

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