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DS31256 数据表(PDF) 77 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 77 Page - Maxim Integrated Products |
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77 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 77 of 183 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently presetn in the RFSBP register and write it to the channel location indicated by the HCID bits. When the device completes the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation completes. Register Name: RFSBP Register Description: Receive FIFO Starting Block Pointer Register Address: 0904h Bit # 7 6 5 4 3 2 1 0 Name RSBP7 RSBP6 RSBP5 RSBP4 RSBP3 RSBP2 RSBP1 RSBP0 Default Bit # 15 14 13 12 11 10 9 8 Name n/a n/a n/a n/a n/a n/a RSBP9 RSBP8 Default Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Starting Block Pointer (RSBP0 to RSBP9). These bits determine which of the 1024 blocks within the receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block Register Name: RFBPIS Register Description: Receive FIFO Block Pointer Indirect Select Register Address: 0910h Bit # 7 6 5 4 3 2 1 0 Name BLKID7 BLKID6 BLKID5 BLKID4 BLKID3 BLKID2 BLKID1 BLKID0 Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name IAB IARW n/a n/a n/a n/a BLKID9 BLKID8 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Block ID (BLKID0 to BLKID9) 0000000000 (000h) = block number 0 0111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive block pointer RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the RFBP register, the IAB bit is set to 0. When the host wishes to write data to the internal receive |
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