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DS31256 数据表(PDF) 93 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 93 Page - Maxim Integrated Products |
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93 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 93 of 183 Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty State empty descriptor empty descriptor empty descriptor read pointer > empty descriptor < write pointer empty descriptor empty descriptor empty descriptor Full Case The receive free queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Therefore, one descriptor must always remain empty. Receive Free-Queue Full State valid descriptor valid descriptor empty descriptor < write pointer read pointer > valid descriptor valid descriptor valid descriptor valid descriptor Table 9-D describes how to calculate the absolute 32-bit address of the read and write pointers for the receive free queue. Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation BUFFER ALGORITHM Absolute Address = Free Queue Base + Write Pointer x 8 Large Absolute Address = Free Queue Base + Read Pointer x 8 Absolute Address = Free Queue Base + Small Buffer Start x 8 + Write Pointer x 8 Small Absolute Address = Free Queue Base + Small Buffer Start x 8 + Read Pointer x 8 Table 9-E. Receive Free-Queue Internal Address Storage REGISTER NAME ADDRESS Receive Free-Queue Base Address 0 (lower word) RFQBA0 0700h Receive Free-Queue Base Address 1 (upper word) RFQBA1 0704h Receive Free-Queue Large Buffer Host Write Pointer RFQLBWP 0710h Receive Free-Queue Large Buffer DMA Read Pointer RFQLBRP 0718h Receive Free-Queue Small Buffer Start Address RFQSBSA 070Ch Receive Free-Queue Small Buffer Host Write Pointer RFQSBWP 0714h Receive Free-Queue Small Buffer DMA Read Pointer RFQSBRP 071Ch Receive Free-Queue End Address RFQEA 0708h Note: Both RFQSBSA and RFQEA are not absolute addresses, i.e., the absolute end address is “Base + RFQEA x 8.” |
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