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DS31256 数据表(PDF) 62 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 62 Page - Maxim Integrated Products |
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62 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 62 of 183 Register Name: BERTC0 Register Description: BERT Control Register 0 Register Address: 0500h Bit # 7 6 5 4 3 2 1 0 Name n/a TINV RINV PS2 PS1 PS0 LC RESYNC Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name IESYNC IEBED IEOF n/a RPL3 RPL2 RPL1 RPL0 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. It must be cleared and set again for a subsequent resynchronization. Note: Bits 2, 3, and 4 must be set, minimum of 64 system clock cycles, before toggling the resync bit (bit 0). Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for subsequent loads. Bit 2/Pattern Select Bit 0 (PS0); Bit 3/Pattern Select Bit 1 (PS1); Bit 4/Pattern Select Bit 2 (PS2) 000 = pseudorandom pattern 2E7 - 1 001 = pseudorandom pattern 2E11 - 1 010 = pseudorandom pattern 2E15 - 1 011 = pseudorandom pattern QRSS (2E20 - 1 with a 1 forced, if the next 14 positions are 0) 100 = repetitive pattern 101 = alternating word pattern 110 = illegal state 111 = illegal state Bit 5/Receive Invert Data Enable (RINV) 0 = do not invert the incoming data stream 1 = invert the incoming data stream Bit 6/Transmit Invert Data Enable (TINV) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Bit 8/Repetitive Pattern Length Bit 0 (RPL0); Bit 9/Repetitive Pattern Length Bit 1 (RPL1); Bit 10/Repetitive Pattern Length Bit 2 (RPL2); Bit 11/Repetitive Pattern Length Bit 3 (RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or 24 (0111) or 30 (1101). |
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